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PCA9641PW 数据表(PDF) 34 Page - NXP Semiconductors |
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PCA9641PW 数据表(HTML) 34 Page - NXP Semiconductors |
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34 / 55 page ![]() PCA9641 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 2.1 — 27 October 2015 34 of 55 NXP Semiconductors PCA9641 2-channel I2C-bus master arbiter 16.1 Specific applications The PCA9641 is a 2-to-1 I2C-bus master arbiter designed for dual masters sharing the same downstream slave devices. Any master can request the downstream bus at any time and PCA9641 will let the master know when it is its turn to control the downstream bus. The master will not overwrite the other master’s transactions, and no advance software is needed. In high reliability I2C-bus applications, the PCA9641 will switch between masters when the downstream bus is free and clear. If the downstream bus hangs, PCA9641 will remotely recover the bus by multiple ways, such as smart initialization, SMBus time-out, remote toggling of SCL and SDA. 16.2 High reliability systems In a typical multipoint application, shown in Figure 22, the two masters (for example, primary and back-up) are located on separate I2C-buses that connect to multiple downstream I2C-bus slave cards/devices via a PCA9641 for non-hot swap applications to provide high reliability of the I2C-bus. I2C-bus commands are sent via the primary or back-up master and either master can take command of the I2C-bus. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices located on the cards. For even higher reliability in multipoint backplane applications, two dedicated masters can be used for every card as shown in Figure 23. Fig 21. Arbitration application aaa-009751 Master 0 M0-Trans3 M0-Trans2 M0-Trans1 I2C M0 PCA9641 ARBITER I2C M1 M0-Trans1 M1-Trans2 Master 1 t1 M0-Trans3 M1-Trans2 Slave 1 Slave 0 t1 M0-Trans2 M0-Trans1 Slave 2 Slave 3 Slave 4 M0-Trans1 Fig 22. High reliability backplane application 002aag820 SCL1 SDA1 SCL0 SDA0 |
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