PCA9641PW datasheet(2/55 Pages) NXP

2 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

2 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O

pins are 3.6 V tolerant.

An active LOW reset input allows the PCA9641A to be initialized. Pulling the RESET pin

LOW resets the I2C-bus state machine and configures the device to its default state as

does the internal Power-On Reset (POR) function.

Features and benefits

 2-to-1 bidirectional master selector

 Channel selection via I2C-bus

 I2C-bus interface logic; compatible with SMBus standards

 2 active LOW interrupt outputs to master controllers

 Active LOW reset input

 Software reset

 Four address pins allowing up to 112 different addresses

 Arbitration active when two masters try to take the downstream I2C-bus at the same

time

 The winning master controls the downstream bus until it is done, as long as it is within

the reserve time

 Bus time-out after 100 ms on an inactive downstream I2C-bus (optional)

 Readable device ID (manufacturer, device type, and revision)

 Bus initialization/recovery function

 Low Ron switches

 Allows voltage level translation between 1.8 V, 2.3 V, 2.5 V, 3.3 V and 3.6 V buses

 No glitch on power-up

 Supports hot insertion

 Software identical for both masters

 Operating power supply voltage range of 2.3 V to 3.6 V

 All I/O pins are 3.6 V tolerant

 Up to 1 MHz clock frequency

 ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per

JESD22-C101

 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

 Packages offered: TSSOP16, HVQFN16

Applications

 High reliability systems with dual masters

 Gatekeeper multiplexer on long single bus

 Bus initialization/recovery for slave devices without hardware reset

 Allows masters without arbitration logic to share resources

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