PCA9641PW datasheet(11/55 Pages) NXP

11 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

11 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

7.4 Power-on reset

When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCA9641

in a reset condition until VDD has reached VPOR. At that time, the reset condition is

released and the PCA9641 registers and I2C-bus/SMBus state machine initialize to their

default states. After that, VDD must be lowered to below VPOR and back up to the

operating voltage for a power-reset cycle.

7.5 Reset input (RESET)

The RESET input can be asserted to initialize the system while keeping the VDD at its

operating level. A reset is accomplished by holding the RESET pin LOW for a minimum of

tw(rst). The PCA9641 registers and I2C-bus/SMBus state machine are set to their default

state once RESET is LOW (0). When RESET is HIGH (1), normal operation resumes and

the I2C downstream bus has no connection to any I2C-bus master.

7.6 Software reset

When granted or non-granted master sends a software reset (see Section 13 “General

call software reset”), PCA9641 will reset all internal registers and:

• If SMBUS_SWRST was enabled before software reset happens, PCA9641 sends

SCL LOW for greater than 35 ms to downstream bus following a soft reset.

• If SMBUS_SWRST was disabled before software reset happens, PCA9641 does not

send SCL LOW to downstream bus following a soft reset.

Fig 6.

Internal register map

002aag817

CONTR 0

STATUS 0

RT 0

CONTR 1

STATUS 1

RT 1

PCA9641

REG#001

REG#010

REG#011

CONTR

STATUS

MASTER 0

SCL_MST0

SDA_MST0

REG#001

REG#010

REG#011

MASTER 1

SCL_MST1

SDA_MST1

INT_STATUS 0

INT_MSK 0

INT_STATUS 1

INT_MSK 1

REG#100

REG#101

INT_STATUS

INT_MSK

REG#100

REG#101

MB_LO 0

MB_LO 1

REG#110

MB_LO

REG#110

ID 0

ID 1

REG#000

MB_HI 0

MB_HI 1

REG#111

MB_HI

REG#111

CONTR

STATUS

INT_STATUS

INT_MSK

MB_LO

MB_HI

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