PCA9641PW datasheet(43/55 Pages) NXP

43 / 55 page

PCA9641

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 27 October 2015

43 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

Fig 31. Definition of timing on the I2C-bus

tSP

tBUF

tHD;STA

tLOW

tHD;DAT

tHIGH

tSU;DAT

tSU;STA

tHD;STA

tSU;STO

SDA

SCL

002aaa986

0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

Rise and fall times, refer to VIL and VIH.

Fig 32. I2C-bus timing diagram

002aab175

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 0

(R/W)

acknowledge

(A)

STOP

condition

(P)

SCL

SDA

tHD;STA

tSU;DAT

tHD;DAT

tBUF

tSU;STA

tLOW

tHIGH

tVD;ACK

tSU;STO

1 / fSCL

tVD;DAT

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

Fig 33. Definition of RESET timing

SDA

SCL

002aae735

trst

50 %

30 %

50 %

tREC;STA

tw(rst)L

RESET

INTn

START

trst

ACK or read cycle

PCA9641PW 数据表(PDF) 43 Page - NXP Semiconductors

PCA9641PW 数据表(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表下载

链接网址

PCA9641PW 数据表(PDF) 43 Page - NXP Semiconductors

PCA9641PW 数据表(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

数据表 下载

链接网址

数据表下载