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PCA9641PW 数据表(PDF) 1 Page - NXP Semiconductors |
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PCA9641PW 数据表(HTML) 1 Page - NXP Semiconductors |
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1 / 55 page  1. General description The PCA9641 is a 2-to-1 I2C master demultiplexer with an arbiter function. It is designed for high reliability dual master I2C-bus applications where correct system operation is required, even when two I2C-bus masters issue their commands at the same time. The arbiter will select a winner and let it work uninterrupted, and the losing master will take control of the I2C-bus after the winner has finished. The arbiter also allows for queued requests where a master requests the downstream bus while the other master has control. A race condition occurs when two masters try to access the downstream I2C-bus at almost the same time. The PCA9641 intelligently selects one winning master and the losing master gains control of the bus after the winning master gives up the bus or the reserve time has expired. Multiple transactions can be done without interruption. The time needed for multiple transactions on the downstream bus can be reserved by programming the Reserve Time register. During the reserve time, the downstream bus cannot be lost. Software reset allows a master to send a reset through the I2C-bus to put the PCA9641’s registers into the power-on reset condition. The Device ID of the PCA9641 can be read by the master and includes manufacturer, device type and revision. When there is no activity on the downstream I2C-bus over 100 ms, optionally the PCA9641 will disconnect the downstream bus to both masters to avoid a lock-up on the I2C-bus. The interrupt outputs are used to provide an indication of which master has control of the bus, and which master has lost the downstream bus. One interrupt input (INT_IN) collects downstream information and propagates it to the two upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the master know if the shared mail box has any new mail or if the outgoing mail has not been read by the other master. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9641. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 3.3 V devices without any additional protection. The PCA9641 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. PCA9641 2-channel I2C-bus master arbiter Rev. 2.1 — 27 October 2015 Product data sheet |
类似零件编号 - PCA9641PW |
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类似说明 - PCA9641PW |
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