PCA9641PW datasheet(14/55 Pages) NXP

14 / 55 page

PCA9641

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Product data sheet

Rev. 2.1 — 27 October 2015

14 of 55

NXP Semiconductors

PCA9641

2-channel I2C-bus master arbiter

IDLE_TIMER_DIS

R/W

After RES_TIME is expired, I2C-bus idle for more

than 100 ms, PCA9641 will disconnect master from

downstream bus and takes away its grant if this

function also applies when there is a grant of a

request with zero value on RES_TIME.

Normal operation.

Enable 100 ms idle timer. After reserve timer

expires or if reserve timer is disabled, if the

downstream bus is idle for more than 100 ms, the

connection between master and downstream bus

will be disconnected.

SMBUS_SWRST

R/W

Non-granted or granted master sends a soft reset,

if this bit is set, PCA9641 sets clock LOW for 35 ms

following reset of all register values to defaults.

Normal operation.

Enable sending SMBus time-out to downstream

bus, after receiving a general call soft reset from

master.

BUS_INIT

R/W

Bus initialization for PCA9641 sends one clock out

and checks SDA signal. If SDA is HIGH, PCA9641

sends a ‘not acknowledge’ and a STOP condition.

The BUS_INIT function is completed. If SDA is

LOW, PCA9641 sends other clock out and checks

SDA again. The PCA9641 will send out 9 clocks

(maximum), and if SDA is still LOW, PCA9641

determines the bus initialization has failed.

Normal operation.

Start initialization on next bus connect function to

downstream bus.

BUS_CONNECT

R/W

Connectivity between master and downstream bus;

the internal switch connects I2C-bus from master to

downstream bus only if LOCK_GRANT = 1.

Do not connect I2C-bus from master to downstream

bus.

Connect downstream bus; the internal switch is

closed only if LOCK_GRANT = 1.

LOCK_GRANT

R only

This is a status read only register bit. Lock grant

status register bit indicates the ownership between

reading master and the downstream bus. If this

downstream bus. If this register bit is zero, the

reading master has not owned the downstream

bus.

This master does not have a lock on the

downstream bus.

This master has a lock on the downstream bus.

Table 8.

CONTR - Control register (pointer address 01h) bit description …continued

POR = 00h.

Legend: * default value

Bit

Symbol

Access

Value

Description

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