PM7367 datasheet(25/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

Pin Name

Type

No.

Function

RBCLK

Tristate

Output

The receive BERT clock signal (RBCLK)

contains the receive bit error rate test clock.

RBCLK is a buffered version of the selected

one of the receive clock signals

(RCLK[31:0]). RBCLK may be tri-stated by

setting the RBEN bit in the FREEDM-32P32

Master BERT Control register low.

TCLK[0]

TCLK[1]

TCLK[2]

TCLK[3]

TCLK[4]

TCLK[5]

TCLK[6]

TCLK[7]

TCLK[8]

TCLK[9]

TCLK[10]

TCLK[11]

TCLK[12]

TCLK[13]

TCLK[14]

TCLK[15]

TCLK[16]

TCLK[17]

TCLK[18]

TCLK[19]

TCLK[20]

TCLK[21]

TCLK[22]

TCLK[23]

TCLK[24]

TCLK[25]

TCLK[26]

TCLK[27]

TCLK[28]

TCLK[29]

TCLK[30]

TCLK[31]

Input

V10

Y11

V11

Y12

V12

Y13

V13

W14

V14

The transmit line clock signals (TCLK[31:0])

contain the transmit clocks for the 32

independently timed links. Processing of

the transmit links is on a priority basis, in

descending order from TCLK[0] to

TCLK[31]. Therefore, the highest rate link

should be connected to TCLK[0] and the

lowest to TCLK[31]. TD[31:0] is updated on

the falling edge of the corresponding

TCLK[31:0] clock.

For channelised T1 or E1 links, TCLK[n]

must be gapped during the framing bit (for

T1 interfaces) or during time-slot 0 (for E1

interfaces) of the TD[n] stream. The

FREEDM-32P32 uses the gapping

information to determine the time-slot

alignment in the transmit stream.

For unchannelised links, TCLK[n] must be

externally gapped during the bits or time-

slots that are not part of the transmission

format payload (i.e. not part of the HDLC

packet).

TCLK[31:3] is nominally a 50% duty cycle

clock between 0 and 10 MHz. TCLK[2:0] is

nominally a 50% duty cycle clock between 0

and 52 MHz. Typical values for TCLK[31:0]

include 1.544 MHz (for T1 links) and 2.048

MHz (for E1 links).

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