PM7367 datasheet(62/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

8.5.1 Master Machine

The GPIC master machine translates requests from the RMAC and TMAC block

interfaces into PCI bus transactions. The GPIC initiates four types of PCI cycles:

memory read (burst or single), memory read multiple, memory read line and

memory write (burst or single). The number of data transfers in any cycle is

controlled by the DMA controllers. The maximum burst size is determined by the

particular data path. A read cycle to the RMAC is restricted to a maximum burst

size of 8 dwords and a write cycle is limited to a maximum of 32. The TMAC

interface has a limit of 32 dwords on a read cycle and 8 on a write cycle.

In response to a DMA controller requesting a cycle, the GPIC must arbitrate for

control of the PCI bus. Before asserting the PCI Request line, the GPIC first

does an internal arbitration to determine the priority of service in the event that

both the RMAC and TMAC are requesting service. The GPIC arbitrates between

the four FIFOs based on either a RMAC priority or a round-robin scheme that is

software selectable. It is possible for all four FIFOs (RMAC read, TMAC read,

RMAC write, TMAC write) to request service simultaneously.

When an external PCI bus arbitrator issues a Grant in response to the Request

from the GPIC, the master state machine monitors the PCI bus to insure that the

previous master has completed its transaction and has released the bus before

beginning the cycle. Once the GPIC has control of the bus, it will assert the

FRAME signal and drive the bus with the address and command. The value for

the address is provided by the selected DMA controller. After the initial data

transfer, the GPIC tracks the address for all remaining transfers in the burst

internally in case the GPIC is disconnected by the target and must retry the

transaction.

The target of the GPIC master burst cycle has the option of stopping or

disconnecting the burst at any point. In the event of a target disconnect the

GPIC will terminate the present cycle and release the PCI bus. If the GPIC is

asserting the REQUEST line at the time of the disconnect, it will remove the

REQUEST for two PCI clock cycles then reassert it. When the PCI bus arbitrator

returns the GRANT, the GPIC will restart the burst access at the next address

and continue until the burst is completed or repeat the sequence if the target

disconnects again.

During burst reads, the GPIC accepts the data without inserting any wait states.

Data is written directly into the read FIFO where the RMAC or TMAC can remove

it at its own rate. During burst writes, the GPIC will output the data without

inserting any wait states, but may terminate the transaction early if the local

master fails to fill the write FIFO with data before the GPIC requires it. (If a write

transaction is terminated early due to data starvation, the GPIC will automatically

PM7367 数据表(PDF) 62 Page - PMC-Sierra, Inc

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