PM7367 datasheet(63/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

initiate a further transaction to write the remaining data when it becomes

available.)

Normally, the GPIC will begin requesting the PCI bus for a write transaction

shortly after data starts to be loaded into the write FIFO by the RMAC or TMAC.

The RMAC, however, is not required to supply a transaction length when writing

packet data and in addition, may insert pauses during the transfer. In the case of

packet data writes by the RMAC, the GPIC will hold off requesting the PCI bus

until the write FIFO has filled up with a number of dwords equal to a

programmable threshold. If the FIFO empties without reaching the end of the

transition, the GPIC will terminate the current transaction and restart a new

transaction to transfer any remaining data when the RMAC signals an end of

transaction. Beginning the PCI transaction before all the data is in the write

FIFO allows the GPIC to reduce the impact of the bus latency on the core

device.

Each master PCI cycle generated by the GPIC can be terminated in three ways:

Completion, Timeout or Master Abort. The normal mode of operation of the GPIC

is to terminate after transferring all the data from the master FIFO selected. As

noted above this may involve multiple PCI accesses because of the inability of

the target to accept the full burst or data starvation during writes. After the

completion of the burst transfer the GPIC will release the bus unless another

FIFO is requesting service, in which case if the GRANT is asserted the GPIC will

insert one idle cycle on the bus and then start a new transfer.

The maximum duration of the a master burst cycle is controlled by the value set

in the LATENCY TIMER register in the GPIC Configuration Register block. This

value is set by the host on boot and is loaded into a counter in the GPIC master

state at the start of each access. If the counter reaches zero and the GRANT

signal has been removed the GPIC will release the bus regardless of whether it

has completed the present burst cycle. This type of termination is referred to as

a Master Time-out. In the case of a Master Time-out the GPIC will remove the

REQUEST signal for two PCI clocks and then reassert it to complete the burst

cycle.

If no target responds to the address placed on the bus by the GPIC after 4 PCI

clocks the GPIC will terminate the cycle and flag the cycle in the PCI Command/

Status Configuration Register as a Master Abort. If the Stop on Error enable

(SOE_E) bit is set in the GPIC Command Register, the GPIC will not process any

more requests until the error condition is cleared. If the SOE_E is not set, the

GPIC will discard the REQUEST and indicate to the local master that the cycle is

complete. This action will result in any write data being lost and any read data

being erroneous.

PM7367 数据表(PDF) 63 Page - PMC-Sierra, Inc

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