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PM7367 数据表(PDF) 65 Page - PMC-Sierra, Inc

部件名 PM7367
功能描述  FRAME ENGINE AND DATA LINK MANAGER
PDF  323 Pages
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制造商  PMC [PMC-Sierra, Inc]
网页  http://www.pmc-sierra.com
标志 PMC - PMC-Sierra, Inc

PM7367 数据表(HTML) 65 Page - PMC-Sierra, Inc

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PM7367 FREEDM-32P32
DATA SHEET
PMC-1991499
ISSUE 2
FRAME ENGINE AND DATA LINK MANAGER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE
51
will perform any byte-realignment required. In order to complete a transfer
involving byte re-alignment, the GPIC may need to add an extra burst cycle to
the PCI transaction.
8.5.3 Target Machine
The GPIC target machine performs all the required functions of a stand alone
PCI target device. The target block performs three main functions. The first is
the target state machine which controls the protocol of PCI target accesses to
the GPIC. The second function is to provide all PCI Configuration registers.
Last, the target block provides a Target Interface to the CBI registers in the other
FREEDM-32P32 blocks.
The GPIC tracks the PCI bus and decodes all addresses and commands placed
on the bus to determine whether to respond to the access. The GPIC responds
to the following types of PCI bus commands only: Configuration read and write,
memory read and write, memory-read-multiple and memory-read-line which are
aliased to memory read and memory-write-and-invalidate which is aliased to
memory write. The GPIC will ignore any access that falls within the address
range but has any other command type.
After accepting a target access as a medium speed device, the FREEDM inserts
one wait state for a configuration read/write and five wait states for other
command types before completing the transaction by asserting TRDYB.
Burst accesses to the GPIC are accepted provided they are of linear type. If a
master makes a memory access to the GPIC with the lower two address bits set
to any value but "00" (linear burst type) the GPIC ignores the cycle. Burst
accesses of any length are accepted, but the FREEDM will disconnect if the
master inserts any wait states during the transaction. The FREEDM will also
disconnect on every read and write access to configuration space after
transferring one Dword of data.
Figure 9 illustrates the GPIC address space.



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