PM7367 datasheet(37/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

Table 3 – Miscellaneous Interface Signals (41)

Pin Name

Type

No.

Function

SYSCLK

Input

The system clock (SYSCLK) provides timing for

the core logic. SYSCLK is nominally a 50% duty

cycle 25 MHz to 33 MHz clock.

RSTB

Input

U14

The active low reset signal (RSTB) signal

provides an asynchronous FREEDM-32P32

reset. RSTB is an asynchronous input. When

RSTB is set low, all FREEDM-32P32 registers are

forced to their default states. In addition,

TD[31:0] are forced high and all PCI output pins

are forced tri-state and will remain high or

tri-stated, respectively, until RSTB is set high.

PMCTEST

Input

V15

The PMC production test enable signal

(PMCTEST) places the FREEDM-32P32 is test

mode. When PMCTEST is set high, production

test vectors can be executed to verify

manufacturing via the test mode interface signals

TA[10:0], TA[11]/TRS, TRDB, TWRB and

TDAT[15:0]. PMCTEST must be tied low in

normal operation.

TCK

Input

The test clock signal (TCK) provides timing for

test operations that can be carried out using the

IEEE P1149.1 test access port. TMS and TDI are

sampled on the rising edge of TCK. TDO is

updated on the falling edge of TCK.

TMS

Input

The test mode select signal (TMS) controls the

test operations that can be carried out using the

IEEE P1149.1 test access port. TMS is sampled

on the rising edge of TCK. TMS has an integral

pull up resistor.

TDI

Input

The test data input signal (TDI) carries test data

into the FREEDM-32P32 via the IEEE P1149.1

test access port. TDI is sampled on the rising

edge of TCK.

TDI has an integral pull up resistor.

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PM7367 数据表(PDF) 37 Page - PMC-Sierra, Inc

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