PM7367 datasheet(98/323 Pages) PMC

98 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

RPDFQEE:

The receive packet descriptor free queue error interrupt enable bit

(RPDFQEE) enables receive packet descriptor free queue error interrupts to

the PCI host. When RPDFQEE is set high, attempts to retrieve an RPDR

when both the large buffer and small buffer free queues are empty will cause

an interrupt to be generated on the PCIINTB output. Interrupts are masked

when RPDFQEE is set low. However, the RPDFQEI bit remains valid when

interrupts are disabled and may be polled to detect RPDR free queue empty

error events.

RPDRQEE:

The receive packet descriptor ready queue error interrupt enable bit

(RPDRQEE) enables receive packet descriptor ready queue error interrupts

to the PCI host. When RPDRQEE is set high, attempts to write an RPDR

when ready queue is ready full will cause an interrupt to be generated on the

PCIINTB output. Interrupts are masked when RPDRQEE is set low.

However, the RPDRQEI bit remains valid when interrupts are disabled and

may be polled to detect RPDR ready queue full error events.

TDQFE:

The transmit packet descriptor free queue write interrupt enable bit (TDQFE)

enables transmit packet descriptor free queue write interrupts to the PCI host.

When TDQFE is set high, writing a programmable number of TDRs to the

TDR Free Queue will cause an interrupt to be generated on the PCIINTB

output. Interrupts are masked when TDQFE is set low. However, the TDQFI

bit remains valid when interrupts are disabled and may be polled to detect

TDR free queue write events.

TDQRDYE:

The transmit descriptor ready queue cache read interrupt enable bit

(TDQRDYE) enables transmit descriptor ready queue cache read interrupts

to the PCI host. When TDQRDYE is set high, reading a programmable

number of TDRs from the TDR Ready Queue will cause an interrupt to be

generated on the PCIINTB output. Interrupts are masked when TDQRDYE is

set low. However, the TDQRDYI bit remains valid when interrupts are

disabled and may be polled to detect TDR ready queue cache read events.

TDFQEE:

The transmit descriptor free queue error interrupt enable bit (TDFQEE)

enables transmit descriptor free queue error interrupts to the PCI host. When

TDFQEE is set high, attempting to write to the transmit free queue while the

queue is full will cause an interrupt to be generated on the PCIINTB output.

Interrupts are masked when TDFQEE is set low. However, the TDFQEI bit

PM7367 数据表(PDF) 98 Page - PMC-Sierra, Inc

PM7367 数据表(HTML) 98 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载