PM7367 datasheet(47/323 Pages) PMC

47 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

8.2.4 Loopback Controller

The loopback controller block implements the channel based diagnostic

loopback function. Every valid data byte belonging to a channel with diagnostic

loopback enabled from the Transmit HDLC Processor / Partial Packet Buffer

block (THDL) is written into a 64 word FIFO. The loopback controller monitors

for an idle time-slot or a time-slot carrying a channel with diagnostic loopback

enabled. If either conditions hold, the current data byte is replaced by data

retrieved from the loopback data FIFO.

8.3 Receive HDLC Processor / Partial Packet Buffer

The Receive HDLC Processor / Partial Packet Buffer block (RHDL) processes up

to 32 synchronous transmission HDLC data streams. Each channel can be

individually configured to perform flag sequence detection, bit de-stuffing and

CRC-CCITT or CRC-32 verification. The packet data is written into the partial

packet buffer. At the end of a frame, packet status including CRC error, octet

alignment error and maximum length violation are also loaded into the partial

packet buffer. Alternatively, a channel can be provisioned as transparent, in

which case, the HDLC data stream is passed to the partial packet buffer

processor verbatim.

There is a natural precedence in the alarms detectable on a receive packet.

Once a packet exceeds the programmable maximum packet length, no further

processing is performed on it. Thus, octet alignment detection, FCS verification

and abort recognition are squelched on packets with a maximum length violation.

An abort indication squelches octet alignment detection, minimum packet length

violations, and FCS verification. In addition, FCS verification is only performed

on packets that do not have octet alignment errors, in order to allow the RHDL to

perform CRC calculations on a byte-basis.

The partial packet buffer is an 8 Kbyte RAM that is divided into 16-byte blocks.

Each block has an associated pointer which points to another block. A logical

FIFO is created for each provisioned channel by programming the block pointers

to form a circular linked list. A channel FIFO can be assigned a minimum of 3

blocks (48 bytes) and a maximum of 512 blocks (8 Kbytes). The depth of the

channel FIFOs are monitored in a round-robin fashion. Requests are made to

the Receive DMA Controller block (RMAC) to transfer, to the PCI host memory,

data in channel FIFOs with depths exceeding their associated threshold.

8.3.1 HDLC Processor

The HDLC processor is a time-slice state machine which can process up to 32

independent channels. The state vector and provisioning information for each

PM7367 数据表(PDF) 47 Page - PMC-Sierra, Inc

PM7367 数据表(HTML) 47 Page - PMC-Sierra, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载