PM7367 datasheet(67/323 Pages) PMC

67 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

8.5.4 CBI Bus Interface

The CBI bus interface provides access to the CBI address space of the

FREEDM-32P32 blocks. The CBI address space is set by the associated BAR in

the PCI Configuration registers.

Write transfers to the CBI space always write all 32 bits provided that at least

one byte enable is asserted. A write command with all byte enables negated will

be ignored. Read transfers always return the 32 bits regardless of the status of

the byte enables, as long as at least one byte enable is asserted. A read

command with all byte enables negated will be ignored.

8.5.5 Error / Bus Control

The Error/Bus Control block monitors signals from both the Target block and

Master Block to determine the direction of the PCI bus pads and to generate or

check parity. After reset, the GPIC sets all bi-directional PCI bus pads to inputs

and monitors the bus for accesses. The Error/Bus control unit remains in this

state unless either the Master requests the PCI bus or the Target responds to a

PCI Master Access. The Error/Bus control unit decodes the state of each state

machine to determine the direction of each PCI bus signal.

All PCI bus devices are required to check and generate even parity across

AD[31:0] and C/BEB[3:0] signals. The GPIC generates parity on Master address

and write data phases; the target generates parity on read data phases. The

GPIC is required to check parity on all PCI bus phases even if it is not

participating in the cycle. But, the GPIC will report parity errors only if the GPIC

is involved in the PCI cycle or if the GPIC detects an address parity error or data

parity is detected in a PCI special cycle. The GPIC updates the PCI

Configuration Status register for all detected error conditions.

8.6 Transmit DMA Controller

The Transmit DMA Controller block (TMAC) is a DMA controller which retrieves

packet data from host computer memory for transmission. The minimum packet

data length is two bytes. The TMAC communicates with the host computer bus

through the master interface connected to PCI Controller block (GPIC) which

translates host bus specific signals from the host to the master interface format.

The TMAC uses the master interface whenever it wishes to initiate a host bus

read or write; in this case, the TMAC is the initiator and the host memory is the

target.

The TMAC and the host exchange information using transmit descriptors (TDs).

The descriptor contains the size and location of buffers in host memory and the

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