PM7367 datasheet(61/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

Caching RPDRs reduces the number of host bus accesses that the RMAC

makes.

Each cache is managed independently. The elements of the cache are

consumed one at a time as they are needed by the RMAC. The RPDR small

buffer cache is reloaded when it is empty and the RMAC requires a new small

buffer RPDR. The large buffer RPDR cache is reloaded when it is empty and the

RMAC requires a new large buffer RPDR. When reloading either of the caches,

the appropriate cache controller will read up to six new elements. The cache

controller may read fewer than six elements if there are fewer than six new

elements available, or the read pointer index is within six elements of the end of

the free queue. If the read pointer is near the end of the free queue, the cache

controller reads only to the end of the queue and does not start reading from the

top of the queue until the next time a reload is required. To do so would require

two host memory transactions and would be of no benefit.

8.5 PCI Controller

The General-Purpose Peripheral Component Interconnect Controller block

(GPIC) provides a 32-bit Master and Target interface core which contains all the

required control functions for Peripheral Component Interconnect (PCI) Bus

Revision 2.1 interfacing. Communications between the PCI bus and other

FREEDM-32P32 blocks can be made through either an internal

asynchronous16-bit bus or through one of two synchronous FIFO interfaces.

One of the FIFO interfaces is dedicated to servicing the Receive DMA Controller

block (RMAC) and the other to the Transmit DMA Controller block (TMAC).

The GPIC supports a 32-bit PCI bus operating at up to 33 MHz and bridges

between the timing domain of the DMA controllers (SYSCLK) and the timing

domain of the PCI bus (PCICLK). By itself, the GPIC does not generate any PCI

bus accesses. All transactions on the bus are initiated by another PCI bus

master or by the core device. The GPIC transforms each access to and from the

PCI bus to the intended target or initiator in the core device. Except for the

configuration space registers and parity generating/checking, the GPIC performs

no operations on the data.

The GPIC is made up of four sections: master state machine, a target state

machine, internal microprocessor bus interface and error/bus controller. The

target and master blocks operate independent of each other. The error/bus

control block monitors the control signals from the target and master blocks to

determine the state of the PCI I/O pads. This block also generates and/or

checks parity for all data going to or coming from the PCI bus. The internal

microprocessor bus interface block contains configuration and status registers

together with the production test logic for the GPIC block.

PM7367 数据表(PDF) 61 Page - PMC-Sierra, Inc

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