PM7367 datasheet(46/323 Pages) PMC

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PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

8.2.1 Line Interface

There are 32 identical line interface blocks in the RCAS. Each line interface

contains a bit counter, an 8-bit shift register and a holding register, that, together,

perform serial to parallel conversion. Whenever the holding register is updated,

a request for service is sent to the priority encoder block. When acknowledged

by the priority encoder, the line interface would respond with the data residing in

the holding register.

To support channelised links, each line interface block contains a time-slot

counter and a clock activity monitor. The time-slot counter is incremented each

time the holding register is updated. The clock activity monitor is a counter that

increments at the system clock (SYSCLK) rate and is cleared by a rising edge of

the receive clock (RCLK[n]). A framing bit (T1) or framing byte (E1) is detected

when the counter reaches a programmable threshold. In which case, the bit and

time-slot counters are initialised to indicate that the next bit is the most significant

bit of the first time-slot. For unchannelised links, the time-slot counter and the

clock activity monitor are held reset.

8.2.2 Priority Encoder

The priority encoder monitors the line interfaces for requests and synchronises

them to the SYSCLK timing domain. Requests are serviced on a fixed priority

scheme where highest to lowest priority is assigned from the line interface

attached to RD[0] to that attached to RD[31]. Thus, simultaneous requests from

RD[m] will be serviced ahead of RD[n], if m < n. When there are no pending

requests, the priority encoder generates an idle cycle. In addition, once every

fourth SYSCLK cycle, the priority encoder inserts a null cycle where no requests

are serviced. This cycle is used by the channel assigner downstream for host

microprocessor accesses to the provisioning RAMs.

8.2.3 Channel Assigner

The channel assigner block determines the channel number of the data byte

currently being processed. The block contains a 1024 word channel provision

RAM. The address of the RAM is constructed from concatenating the link

number and the time-slot number of the current data byte. The fields of each

RAM word include the channel number and a time-slot enable flag. The time-slot

enable flag labels the current time-slot as belonging to the channel indicted by

the channel number field.

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