PM7367 datasheet(83/323 Pages) PMC

83 / 323 page

PM7367 FREEDM-32P32

DATA SHEET

PMC-1991499

ISSUE 2

FRAME ENGINE AND DATA LINK MANAGER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE

Figure 15 – Partial Packet Buffer Structure

16 bytes

Partial Packet

Buffer RAM

Block 511

Block 0

Block 1

Block 2

Block 3

Block 511

Block 0

Block 1

Block 2

Block 3

Block

Pointer RAM

Block 200

0x03

0xC8

0x01

The writer and reader determine empty and full FIFO conditions using flags.

Each block in the partial packet buffer has an associated flag. The writer sets

the flag after the block is written and the reader clears the flag after the block is

read. The flags are initialized (cleared) when the block pointers are written using

indirect block writes. The reader declares a channel FIFO under-run whenever it

tries to read data from a block without a set flag.

The FIFO algorithm of the partial packet buffer processor is based on per-

channel software programmable transfer size and free space trigger level.

Instead of tracking the number of full blocks in a channel FIFO, the processor

tracks the number of empty blocks, called free space, as well as the number of

end of packets stored in the FIFO. Recording the number of empty blocks

instead of the number of full blocks reduces the amount of information the

roamer must store in its state RAM.

The partial packet roamer records the FIFO free space and end-of-packet count

for all channel FIFOs. When the reader signals that a block has been read, the

roamer increments the FIFO free space and sets a per-channel request flag if

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