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PM7367 数据表(PDF) 12 Page - PMC-Sierra, Inc |
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PM7367 数据表(HTML) 12 Page - PMC-Sierra, Inc |
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12 / 323 page ![]() PM7367 FREEDM-32P32 DATA SHEET PMC-1991499 ISSUE 2 FRAME ENGINE AND DATA LINK MANAGER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMER’S INTERNAL USE xi FIGURE 23 – CHANNELISED T1 RECEIVE LINK TIMING ............................285 FIGURE 24 – CHANNELISED E1 RECEIVE LINK TIMING ............................285 FIGURE 25 – UNCHANNELISED TRANSMIT LINK TIMING..........................286 FIGURE 26 – CHANNELISED T1 TRANSMIT LINK TIMING..........................286 FIGURE 27 – CHANNELISED E1 TRANSMIT LINK TIMING .........................287 FIGURE 28 – PCI READ CYCLE ....................................................................288 FIGURE 29 – PCI WRITE CYCLE ..................................................................290 FIGURE 30 – PCI TARGET DISCONNECT ....................................................291 FIGURE 31 – PCI TARGET ABORT................................................................291 FIGURE 32 – PCI BUS REQUEST CYCLE ....................................................292 FIGURE 33 – PCI INITIATOR ABORT TERMINATION ...................................293 FIGURE 34 – PCI EXCLUSIVE LOCK CYCLE ...............................................294 FIGURE 35 – PCI FAST BACK TO BACK.......................................................296 FIGURE 36 – RECEIVE BERT PORT TIMING ...............................................296 FIGURE 37 – TRANSMIT BERT PORT TIMING .............................................297 FIGURE 38 – RECEIVE LINK INPUT TIMING ................................................302 FIGURE 39 – BERT INPUT TIMING ...............................................................302 FIGURE 40 – TRANSMIT LINK OUTPUT TIMING..........................................304 FIGURE 41 – BERT OUTPUT TIMING ...........................................................304 FIGURE 42 – PCI INTERFACE TIMING .........................................................305 FIGURE 43 – JTAG PORT INTERFACE TIMING............................................306 FIGURE 44 – 272 PIN PLASTIC BALL GRID ARRAY (PBGA) .......................308 |
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