MCP8021 datasheet(24/66 Pages) MICROCHIP

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MCP8021/2

DS20006265D-page 24

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4.4.2

STANDBY STATE

Standby state is entered when the OE pin goes low for

longer than 1 ms and the SLEEP Configuration bit is

inactive. When Standby mode is entered, the following

subsystems are disabled:

• High-side gate drives (HSA, HSB, HSC) forced low

• Low-side gate drives (LSA, LSB, LSC) forced low

•VBOOT LDO

• Charge pump

• Operational amplifiers if CFG0[6] = 1 (MCP8022)

The VREG LDO, operational amplifiers (if CFG0[6] = 0)

and DE2 communications stay active.

The total current consumption of the device when OE

is inactive (device disabled) stays within the “Standby

mode input quiescent current” limits specified in the

device characteristics table.

4.4.3

SLEEP MODE

Sleep mode is entered when both a SLEEP command

is sent to the device via DE2 communications and the

OE pin is low. The two conditions may occur in any

order. The transition to Sleep mode occurs after the

last of the two conditions occurs. The SLEEP bit in the

CFG0 Configuration register indicates when the

device should transition to a low-power mode. The

device will operate normally until the OE pin is transi-

tioned low by an external device. At that point in time,

the SLEEP bit value determines whether the device

transitions to Standby mode or low-power Sleep mode.

The supply current (ISUP) during Sleep mode will typi-

cally be 5 μA. When Sleep mode is activated, most

functions will be shut off, including the VREG LDO.

Only the Power-on Reset monitor and minimal state

machine will remain active to detect a wake-up event.

This indicates that the host processor will be shut

down if the host is using the VREG LDO regulator for

power. The device will stay in the low-power Sleep

mode until either of the following conditions is met:

• The WAKE pin transitions high after being in a low

state lasting longer than tWAIT_SETUP

• Power is cycled

The MCP8021/2 devices are not required to retain

configuration data while in Sleep mode. When exiting

Sleep mode, the host should send a new configuration

message to configure the device if the default configu-

ration values are not desired. The same configuration

sequence used during power-up may be used when

exiting Sleep mode.

When activated, Sleep mode will always be entered

regardless of any active Fault. This allows a transition

to Sleep mode when the host is powered by the VREG

LDO and the regulator is in an unreliable state. The

SLEEP bit in the Configuration register will be ignored

at power-up until the system has enabled the VREG

LDO and the VREG LDO has entered regulation.

4.5

Faults

4.5.1

FAULT PIN OUTPUT (FAULT)

The FAULT pin is used as a Fault indicator. The pin is

capable of sinking a minimum of 1 mA of current while

maintaining less than 50 mV of voltage across the

output. An external pull-up resistor to the logic supply

is required.

The open-drain FAULT pin transitions low when a

Fault occurs. Table 4-1 lists the Faults that activate the

FAULT signal. Warnings do not activate the FAULT

signal; Table 4-2 lists the warnings.

4.5.2

FAULT HANDLING SEQUENCE

When a Fault occurs, the following steps will occur in

sequence.

The gate drive outputs will be immediately

turned off.

The FAULT pin output will go low.

A message will be sent via the DE2

communications link.

The VREG LDO will be disabled immediately if

the Fault is a VDD undervoltage shutdown

(UVSHDNACT) Fault.

The VREG LDO will be disabled 5 ms after the

DE2

message

has

been

sent

for

overtemperature shutdown (OTSHDN) Fault.

4.5.3

FAULT INDICATOR

A FAULT indicator bit resides in the STAT0 register.

The bit is the logical ‘OR’ of all of the Fault bits in the

two status registers. Warnings are not included in the

FAULT indicator bit.

The FAULT bit will allow the user to read the STAT0

system. If the bit is set, then the user may request the

STAT1 message and interrogate the bits of both status

messages to determine what Faults exist.

The Faults that are logically OR’d together to generate

the FAULT bit are as follows:

• STAT0:OTPF

• STAT0:UVLOF

• STAT0:OVLOF

•STAT1:REGUVF

•STAT1:XUVLOF

•STAT1:XOCPF

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