MCP8021 datasheet(17/66 Pages) MICROCHIP

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DS20006265D-page 17

MCP8021/2

3.1

Communications Port (DE2)

Open-drain communications node. The DE2 commu-

nications is a half-duplex, 9600 baud, 8-bit, no parity

communications link. The open-drain DE2 pin must be

pulled high by an external pull-up resistor. The pin has

a minimum drive capability of 1 mA with a VDE2 of

50 mV when driving low.

3.2

Low-Side PWM Inputs

(PWMAL, PWMBL, PWMCL)

Digital PWM inputs for low-side driver control. Each input

has a pull-down resistor. The PWM signals may contain

dead-time timing or the system may use the CFG2

Configuration register to set the dead time.

3.3

High-Side PWM Inputs

(PWMAH, PWMBH, PWMCH)

Digital PWM inputs for high-side driver control. Each

input has a pull-down resistor. The PWM signals may

contain dead-time timing or the system may use the

CFG2 Configuration register to set the dead time.

3.4

Output Enable Input (OE)

The Output Enable input pin is used to enable/disable

the output driver and the on-board functions. When

OE is high, all device functions are enabled. When OE

is low, the device operates in Standby or Sleep mode.

When Standby mode is active, the VBOOT output

supply and charge pump are disabled. The operational

amplifiers in the MCP8022 are also disabled if the

OPAMP bit in the CFG0 Configuration register is set.

The high-side and low-side gate drive outputs are all

set to a low state within 100 ns of OE going low. The

device transitions to Standby or Sleep mode, 1 ms

after OE goes low.

The OE pin may be used to clear any hardware Faults.

When a Fault occurs, the OE input may be used to

clear the Fault by setting the pin low and then high

again. The Fault is cleared by the rising edge of the

OE signal if the hardware Fault is no longer active.

The OE pin is used to enable Sleep mode when the

SLEEP bit in the CFG0 Configuration register is set to

a ‘1’. OE must be low for a minimum of 1 ms before

the transition to Standby or Sleep mode will occur. This

allows time for OE to be toggled, to clear any Faults,

without going into Sleep mode.

The OE pin has an internal pull-down resistor.

3.5

Fault Output (FAULT)

Fault output pin. The latched open-drain output will go

low while a Fault is active. Table 4-4 shows the Faults

that cause the FAULT pin to go low. The pin will stay

low until the Fault is inactive and the OE pin is toggled,

from low-to-high, to clear the internal Fault latch.

The FAULT pin is able to sink 1 mA of current while

maintaining less than a 50 mV drop across the output.

The FAULT pin will also be active (low) upon initial

power-up until the state machine completes the VREG

state. This may be used to signal an external host that

the driver is ready.

3.6

Power Ground (PGND),

Exposed Pad (EP)

Device ground. The PCB ground traces should be

short, wide and form a star pattern to the power

source. The Exposed Pad (EP) must be soldered to

the PCB. The PCB area below the EP should be a

copper pour with thermal vias to help transfer heat

away from the device.

3.7

Operational Amplifier Outputs

(OUT1, OUT2, OUT3) (MCP8022)

Operational amplifier outputs. These general purpose

amplifiers may be used for current sense gain. The

amplifiers are disabled when OE = 0 and the OPAMP

bit in the CFG0 Configuration register is set.

3.8

Operational Amplifier Inputs

(IN1+/-, IN2+/-, IN3+/-) (MCP8022)

Operational amplifier inverting and noninverting inputs.

Used in conjunction with the corresponding amplifier

OUTx pin to set amplifier gain. The amplifiers are dis-

abled in Standby mode when OE = 0 and the OPAMP

bit in the CFG0 Configuration register is set.

3.9

Wake Input (WAKE)

The WAKE pin has an internal pull-down resistor. The

device will awaken from Sleep mode, on the rising

edge of the WAKE pin, after detecting a low state

lasting > tWAIT_SETUP on the pin. The WAKE pin is

capable of operating at voltage levels up to VDD.

3.10

Motor Phase Inputs

(PHA, PHB, PHC)

Phase signals from the motor. These signals provide

high-side N-channel MOSFET driver bias reference

and Back EMF sense input. The phase signals are

also used with the bootstrap capacitors to provide a

high-side gate drive via the VBx inputs.

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