MCP8021 datasheet(27/66 Pages) MICROCHIP

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DS20006265D-page 27

MCP8021/2

4.6

Motor Control Unit

The motor control unit is comprised of the following:

• External Drive for a 3-Phase Bridge with

NMOS/NMOS MOSFET Pairs

• MOSFET Driver Undervoltage Lockout

• External MOSFET Short-Circuit Current

•FAULT Pin Output

• Cross Conduction Protection

• Programmable Dead Time

• Programmable Blanking Time

• Three General Purpose Operational Amplifiers

(MCP8022)

4.6.1

EXTERNAL DRIVE FOR A 3-PHASE

BRIDGE WITH NMOS/NMOS

MOSFET PAIRS

Each motor phase is driven with external NMOS/

NMOS MOSFET pairs. These are controlled by a low-

side and a high-side gate driver. The gate drivers are

controlled by the digital input pins, PWM[A:C]H/L. A

logic high turns the associated gate driver on and a

logic low turns the associated gate driver off. The

PWM[A:C]H/L digital inputs are equipped with internal

pull-down resistors.

The low-side gate drivers are biased by the VBOOT

regulator output, referenced to ground. The high-side

gate drivers are a floating drive biased by a bootstrap

capacitor circuit. The bootstrap capacitor is charged by

the VBOOT regulator whenever the accompanying

low-side MOSFET is turned on.

The high-side and low-side driver outputs all go to a low

state whenever there is a Fault, when OE = 0 for more

than 1 ms or when Sleep mode is active, regardless of

the PWM[A:C]H/L inputs.

The gate driver output stages have lower dynamic

RDSONDYN in the time frame up to 1 ms after output

activation. This is the relevant drain source on resis-

tance for charging or discharging the external MOSFET

gates.

After elapsing 1 ms or later, the high-side gate driver,

RDSON, increases slightly up to the static RDSON value.

4.6.2

MOSFET GATE DRIVE

UNDERVOLTAGE LOCKOUT (UVLO)

The MOSFET gate drive undervoltage lockout Fault

detection monitors the available voltage used to drive

the external MOSFET gates. The Fault detection is only

active while the driver is actively driving the external

MOSFET gate. Any time the driver bias voltage is below

the gate drive undervoltage lockout threshold (VDUVLO)

for a time longer than specified by the tDUVLO parameter,

the driver will not turn on when commanded on. A driver

Fault will be indicated to the host microcontroller on the

FAULT open-drain output pin and also via a DE2 com-

munications Status_1 message. This is a latched

Fault. Clearing the Fault requires either removal of

device power or disabling and re-enabling the device

via the device Output Enable (OE) input. The

EXTUVLO bit in the CFG0 register is used to enable or

disable the driver undervoltage lockout feature. This

protection feature prevents the external MOSFETs from

being controlled with a gate voltage not suitable to fully

enhance the device.

4.6.3

EXTERNAL MOSFET

SHORT-CIRCUIT CURRENT OCP

Short-circuit protection monitors the voltage across the

external MOSFETs during an on condition. The high-

side driver voltage is measured from VDD to PH[A:C].

The low-side driver voltage is measured from PH[A:C] to

ground. If a monitored voltage rises above a user-

configurable threshold after the driver HS[A:C] or

LS[A:C] output voltage has been driven high, all drivers

will be turned off. A driver Fault will be indicated to the

host microcontroller on the open-drain FAULT output pin

and also via a DE2 communications Status_1 mes-

sage. This is a latched Fault. Clearing the Fault requires

either removal of device power or toggling the OE input

pin low-to-high. This protection feature helps detect

internal motor failures, such as winding to case shorts.

The short-circuit voltage may be set via a DE2

Set_Cfg_0 message. The EXTOC[1:0] bits of the

CFG0 register are used to select the voltage level for

the short-circuit comparison. If a monitored voltage dif-

ferential between VDD and PH[A:C], or between

PH[A:C] and PGND, exceeds the selected voltage level

when the MOSFET gate drive is active, a Fault will be

triggered. The selectable voltage levels are 250 mV,

500 mV, 750 mV and 1000 mV. The EXTSC bit of the

CFG0 register is used to enable or disable the

MOSFET driver short-circuit detection.

4.6.4

GATE CONTROL LOGIC

The gate control logic enables level shifting of the

digital inputs, polarity control and cross conduction

protection.

4.6.4.1

Cross Conduction Protection

If both MOSFETs in the same half-bridge are

commanded on by the digital PWM inputs, both will be

turned off.

Note:

The driver short-circuit protection is

dependent on application parameters. A

configuration message is provided for a

set number of threshold levels. The

MOSFET gate drive UVLO and short-

circuit protection features have the option

to be disabled.

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