MCP8021 datasheet(12/66 Pages) MICROCHIP

12 / 66 page

MCP8021/2

DS20006265D-page 12

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TEMPERATURE SPECIFICATIONS

Parameter

Sym.

Min.

Typ.

Max.

Units

Conditions

Temperature Ranges (Note 1)

Specified Temperature Range

-40

—

+150

°C

Operating Temperature Range

-40

—

+165

°C

Storage Temperature Range

-55

—

+165

°C

Package Thermal Resistances

5 mm x 5 mm 28-Lead VQFN

JA

—

°C/W 4-Layer JC51-7 standard board,

natural convection

JC

—10

—

5 mm x 5 mm 40-Lead VQFN

JA

—

°C/W 4-Layer JC51-7 standard board,

natural convection

JC

—10

—

4.4 mm 28-Lead TSSOP-EP,

0.65 mm Pitch

JA

—

°C/W 4-Layer JC51-7 standard board,

natural convection

JC

—5

—

4.4 mm 38-Lead TSSOP-EP,

0.50 mm Pitch

JA

—

°C/W 4-Layer JC51-7 standard board,

natural convection

JC

—5

—

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the

maximum allowable power dissipation will cause the device operating junction temperature to exceed the

maximum +165°C rating. Sustained junction temperatures above +165°C can impact the device reliability.

ESD, SUSCEPTIBILITY, SURGE AND LATCH-UP TESTING

Parameter

Standard and Test Condition

Value

Input Voltage Surges

ISO 16750-2

40V for 500 ms

ESD HBM with 1.5 k

/100 pF

CEI/IEC 60749-26: 2006

AEC-Q100-002-Ref E

JEDEC JS-001-2017

±2 kV

ESD CDM – Corner Pins

ANSI/ESD-STM5.3.1-2009

CDM13073

AEC-Q100-011-Ref_B

±750V

ESD CDM – All Other Pins

ANSI/ESD-STM5.3.1-2009

CDM13073

AEC-Q100-011-Ref_B

±500V

Latch-Up Susceptibility

AEC Q100-004, 150°C

JEDEC JESD78

> 100 mA

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