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MCP8021 数据表(PDF) 32 Page - Microchip Technology

部件名 MCP8021
功能描述  3-Phase Brushless DC (BLDC) Motor Gate Driver with Power Module, Sleep Mode, Op Amps
PDF  66 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

MCP8021 数据表(HTML) 32 Page - Microchip Technology

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MCP8021/2
DS20006265D-page 32
 2020-2024 Microchip Technology Inc. and its subsidiaries
The PCON bits of the STAT0 register will be set every
time the device restarts due to various events (see
Table 4-3). When the driver resumes operation, a single
unsolicited STATUS_0 message will be sent to the host
indicating a Reset has occurred. The message will be
sent five milliseconds (5 ms) after the VREG LDO has
reached its active state. The host should check the
PCON bits to determine the cause of the power cycle.
In all cases, the configuration data may have been lost
and should be re-sent to the driver. The PCON flags are
reset by a host STATUS_0 request message. If the host
misses the unsolicited STATUS_0 message at start-up,
the host may manually request the status by sending a
STATUS_0 message to the driver. The PCON bits of the
STAT0 register will contain the source of the Power-on
Reset until the STAT0 register is requested by the host.
4.8.7.4
SET_CFG_2
There is a SET_CFG_2 message that is sent by the host
to the MCP8021/2 devices to configure the driver current
limit blanking time. The SET_CFG_2 message may be
sent to the devices at any time. The host is responsible
for making sure the system is in a state that will not be
compromised by sending the SET_CFG_2 message.
The SET_CFG_2 message format is indicated in
Table 4-6. The response is indicated in Table 4-7.
4.8.7.5
GET_CFG_2
There is a GET_CFG_2 message that is sent by the
host to the MCP8021/2 devices to retrieve the device
Configuration Register #2. The GET_CFG_2 message
format is indicated in Table 4-6. The response is
indicated in Table 4-7.
FIGURE 4-4:
DE2 Packet Format.
FIGURE 4-5:
DE2 Packet Timing.
STOP
START
DE2
Message Format
B0
B1
B2
B3
B4
B5
B6
B7
T = 1/Baud Rate (bit cell period)
Detect Start Bit by Sensing
Transition from Logic ‘1’ to Logic ‘0’
TS = T/16 (oversampled bit cell period)
Receiver Samples the Incoming Data
Using x16 Baud Rate Clock
TSTART = 1.5T – Uncertainty on Start
Detection (worst-case: 2x TS)
Sample Incoming Data
at the Bit Cell Center
START
TSTART
TS
STOP
B0
B1
B4
B3
B2
B5
B6
B7



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