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VL6624 数据表(PDF) 92 Page - STMicroelectronics |
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VL6624 数据表(HTML) 92 Page - STMicroelectronics |
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92 / 106 page  Electrical characteristics VL6624/VS6624 92/106 Table 50. Timing specification(1) Symbol Parameter Standard mode Fast mode Unit Min. Max. Min. Max. fSCL SCL clock frequency 0 100 0 400 kHz tHD;STA Hold time for a repeated start 4.0 - 0.6 - μs tLOW LOW period of SCL 4.7 - 1.3 - μs tHIGH HIGH period of SCL 4.0 - 0.6 - μs tSU;STA Set-up time for a repeated start 4.7 - 0.6 - μs tHD;DAT Data hold time (1) 300 - 300 - ns tSU;DAT Data Set-up time (1) 250 - 100 - ns tr Rise time of SCL, SDA - 1000 20+0.1Cb (2) 300 ns tf Fall time of SCL, SDA - 300 20+0.1Cb (2) 300 ns tSU;STO Set-up time for a stop 4.0 - 0.6 - μs tBUF Bus free time between a stop and a start 4.7 - 1.3 - μs Cb Capacitive Load for each bus line - 400 - 400 pF VnL Noise Margin at the LOW level for each connected device (including hysteresis) 0.1 VDD - 0.1 VDD - V VnH Noise Margin at the HIGH level for each connected device (including hysteresis) 0.2 VDD - 0.2 VDD - V 1. All values are referred to a VIHmin = 0.9 VDD and VILmax = 0.1 VDD 2. Cb = capacitance of one bus line in pF |
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