VL6624 datasheet(29/106 Pages) STMICROELECTRONICS

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VL6624/VS6624

Data synchronization methods

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Mode 2 Logical DMA channels

The purpose of logical channels is to separate different data flows which are interleaved in

the data stream, in the case of the VS6624 this allows the identification of the pipe setup

bank used for an image frame. The DMA channel identifier number is directly encoded in the

4-byte mode2 embedded sync codes. The receiver can then monitor the DMA channel

identifier and de-multiplex the interleaved video streams to their appropriate DMA channel.

The bChannelID register can have the value 0 to 6. The DMA channel identifier must be fully

programmable to allow the host to configure which DMA channels the different video data

stream use.

●

Logical channel control

The channel identifier is a part of Mode2 synchronization code, upper four bits of last byte of

synchronization code.

Figure 13. illustrates the synchronization code with logical channel

identifiers.

Figure 13. Mode 2 frame structure (VGA example)

VSYNC and HSYNC

The VL6624/VS6624 can provide two programmable hardware synchronization signals:

VSYNC and HSYNC. The position of these signals within the output frame can be

programmed by the user or an automatic setting can be used where the signals track the

active video portion of the output frame regardless of its size.

Horizontal synchronization signal (HSYNC)

The HSYNC signal is controlled by the bHSyncSetup register. The following options are

available:

●

enable/disable

●

select polarity

●

all lines or active lines only

●

manual or automatic

000

DC LC

DMA Channel Number

Valid channels = 0 to 6

Line code

0x0 = Line Start

0x1 = Line End

0x2 = Frame Start

0x3 = Frame End

32-bit embedded mode 2 sync code

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