VL6624 datasheet(30/106 Pages) STMICROELECTRONICS

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Data synchronization methods

VL6624/VS6624

30/106

In automatic mode the HSYNC signal envelops all the active video data on every line in the

output frame regardless of the programmed image size. Line codes (if selected) fall outside

the HSYNC envelope as shown in

Figure 14.

Figure 14. HSYNC timing example

If manual mode is selected then the pixel positions for HSYNC rising edge and falling edge

are programmable. The pixel position for the rising edge of HSYNC is programmed in the

bHSyncRising registers. The pixel position for the falling edge of HSYNC is programmed in

the bHSyncFalling registers.

Vertical synchronization (VSYNC)

The VSYNC signal is controlled by the bSyncSetup register. The following options are

available:

●

enable/disable

●

select polarity

●

manual or automatic

In automatic mode the VSYNC signal envelops all the active video lines in the output frame

regardless of the programmed image size as shown in

Figure 15.

SAV Code

EAV Code

ACTIVE VIDEO DATA

hsync=1

EAV Code

BLANKING DATA

hsync=0

00 00 XY 80 10 80 10 80 10

80 10

00 00 XY

D0 D1 D2 D3 D0 D1 D2 D3

D2 D3 FF 00 00 XY

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