VL6624 datasheet(31/106 Pages) STMICROELECTRONICS

部件名	VL6624

功能描述	1.3 Megapixel single-chip camera module

PDF	106 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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31 / 106 page

VL6624/VS6624

Data synchronization methods

31/106

Figure 15. VSYNC timing example

If manual mode is selected then the line number for VSYNC rising edge and falling edge is

programmable. The rising edge of VSYNC is programmed in the bVsyncRisingLine

registers, the pixel position for VSYNC rising edge is programmed in the bVsyncRisingPixel

registers. Similarly the line count for the falling edge position is specified in the

bVsyncFallingLine registers, and the pixel count is specified in the bVsyncFallingPixel

registers.

Pixel clock (PCLK)

The PCLK signal is controlled by the

Output formatter control register. The following options

are available:

●

enable/disable

●

select polarity

●

select starting phase

●

qualify/don’t qualify embedded synchronization codes

●

enable/disable during horizontal blanking

BLANKING

V=1

V=0

V=1

V=0

vsync

ACTIVE

VIDEO

ACTIVE

VIDEO

VL6624 数据表(PDF) 31 Page - STMicroelectronics

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