VL6624 datasheet(34/106 Pages) STMICROELECTRONICS

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Getting started

VL6624/VS6624

34/106

Getting started

Initial power up

Before any communication is possible with the VL6624/VS6624 the following steps must

take place:

Apply VDD (1.8V or 2.8V)

Apply AVDD (2.8V)

Apply an external CLOCK (6.5MHz to 54MHz)

Assert CE line HIGH

These steps can all take place simultaneously. After these steps are complete a delay of

200 µs is required before any I²C communication can take place, see

Figure 3: Power up

sequence.

Minimum startup command sequence

Enable the microprocessor - before any commands can be sent to the

VL6624/VS6624, the internal microprocessor must be enabled by writing the value

0x02 to the MicroEnable register 0xC003 found in the

Low level control registers

Section.

Enable the digital I/O - after power up the digital I/O of the VL6624/VS6624 is in a high-

impedance state (‘tri-state’). The I/O are enabled by writing the value 0x01 to the

DIO_Enable register 0xC044 found in the

Low level control registers Section.

The user can then program the system clock frequency and setup the required output

format before placing the VL6624/VS6624 in RUN mode by writing 0x02 to the

Host

interface manager control register 0x0180.

The above three commands represent the absolute minimum required to get video data

output.

The default configuration results in an output of SXGA, 15 fps, YUV data format with ITU

embedded codes requiring a external clock frequency of 12MHz.

In practice the user is likely to require to write some additional setup information prior to

receive the required data output.

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