VL6624 datasheet(10/106 Pages) STMICROELECTRONICS

10 / 106 page

System architecture

VL6624/VS6624

10/106

System architecture

The VS6624 consists of the following main blocks:

●

SXGA-sized pixel array

●

Video timing generator

●

Video pipe

●

Statistics gathering unit

●

Clock generator

●

Microprocessor

A simplified block diagram is shown

Figure 1.

VL6624/VS6624 simplified block diagram

3.1

Operation

A video timing generator controls a SXGA-sized pixel array to produce raw bayer images.

The analogue pixel information is digitized and passed into the video pipe. The video pipe

contains a number of different functions (explained in detail later). At the end of the video

pipe data is output to the host system over an 8-bit parallel interface along with qualification

signals.

The whole system is controlled by an embedded microprocessor that is running firmware

stored in an internal ROM. The external host communicates with this microprocessor over

an I²C interface. The microprocessor does not handle the video data itself but is able to

control all the functions within the video pipe. Real-time information about the video data is

gathered by a statistics engine and is available to the microprocessor. The processor uses

Microprocessor

SDA

SCL

AVDD

HSYNC

PCLK

D[0:7]

CLK

VSYNC

Clock

Generator

I²C

Statistics

Gathering

Video Timing

Generator

RESET

VREG

VDD

I²C Interface

FSO

GND

SXGA

Pixel

Array

Video Pipe

VL6624 数据表(PDF) 10 Page - STMicroelectronics

VL6624 数据表(HTML) 10 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载