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VL6624 数据表(PDF) 94 Page - STMicroelectronics |
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VL6624 数据表(HTML) 94 Page - STMicroelectronics |
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94 / 106 page  Electrical characteristics VL6624/VS6624 94/106 13.7 Parallel data interface timing VL6624/VS6624 contains a parallel data output port (D[7:0]) and associated qualification signals (HSYNC, VSYNC, PCLK and FSO). This port can be enabled and disabled (tri-stated) to facilitate multiple camera systems or bit-serial output configurations. The port is disabled (high impedance) upon reset. Figure 36. Parallel data output video timing Table 51. Parallel data interface timings Symbol Description Min. Max. Unit fPCLK PCLK frequency 54 MHz tPCLKL PCLK low width [1/2*(1/fPCLK)] - 3.9 [1/2*(1/fPCLK)] + 3.9 ns tPCLKH PCLK high width [1/2*(1/fPCLK)] - 3.9 [1/2*(1/fPCLK)] + 3.9 ns tDV PCLK to output valid -5.15 1.62 ns tPCLKL tPCLKH 1/fPCLK PCLK D[0:7] HSYNC, polarity = 0 tDV Valid VSYNC |
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