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VL6624 数据表(PDF) 32 Page - STMicroelectronics |
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VL6624 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 106 page  Data synchronization methods VL6624/VS6624 32/106 Figure 16. QCLK options The YUV, RGB and bayer timings are represented on Figure 17, with the associated qualifying pclk clock. The output clock rate is effectively halved for the bayer 8-bit and YUV4:0:0 modes where only one byte of output data is required per pixel. Figure 17. Qualification clock D0 D1 D2 data Negative edge PCLK Negative edge Positive edge Positive edge None-active level - Low None-active level - High Yn Cbn,n+1 Yn+1 Crn,n+1 YCbCr Data[7:0] Data[7:0] RGB565 Cbn+2,n+3 RGB444 Pix0_lsb Pix0_msb Pix1_lsb Pix1_msb Pix2_lsb Data[7:0] Bayer 10-Bit Pix0_lsb Pix0_msb Pix1_lsb Pix1_msb Pix2_lsb Data[7:0] Bayer 8-Bit Pix0 Pix1 Pix2 Data[7:0] YUV 4:0:0 Pix0 Pix1 Pix2 16-bit data output formats - 2 bytes per pixel 8-bit data output formats- 1 byte per pixel PCLK PCLK PCLK PCLK PCLK |
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