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VL6624 数据表(PDF) 33 Page - STMicroelectronics |
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VL6624 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 106 page  VL6624/VS6624 Data synchronization methods 33/106 Master / Slave operation of PLCK In normal operation VS6624 acts as a master. PCLK is independent of the input clock frequency and does not have a determined phase relation to the input clock. In SLAVE operation the input clock frequency is the same as the output clock frequency and the output data is guaranteed with a certain phase relationship to the input clock. Internally, the VS6624 uses clocks generated from the internal PLL, but a retiming stage is used to re- sync the output to the input clock. In this output mode, derating is not possible. |
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