SAP5SD-B-G1-R datasheet(32/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

5.8.

Data Port and DSTBn

5.8.1.

Timing of Data I/O and DSTBn

Every data pin (D0 to D3) contains an NMOS open-drain output driver as well as a high-voltage, high-impedance

input stage. Received output data is stored in the Data Output Register and subsequently forwarded to the data

pins. A specific time (tDI-latch) after new output data has been written to the port the input data is sampled.

The availability of new output data is signaled by the Data Strobe (DSTBn) signal as shown in Figure 5.3. The

DSTBn pin has an additional reset input function, which is described further in section 5.13.

Any SAP5 reset sets the Data Output Register to FHEX and forces the data output drivers to the high-impedance

state. Simultaneously, a Data Strobe is generated with the same tsetup timing and tDSTBn pulse width as would be

used to drive new output data.

Table 5.10 Timing for Data Port Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNIT

Output data is valid after DSTBn high/low edge

tSTB

0.0

1.5

µs

Output driver is at high impedance state after DSTBn low/high

thold

0.2

1.0

µs

Pulse width of Data Strobe (DSTBn)

tDSTBn

6.0

6.8

µs

Acceptance of input data

tDI-latch

10.5

12.5

µs

Parameter is only valid if the respective data port is configured as an I/O pin.

The timing of the resulting voltage signal also depends on the external pull-up resistor.

The input data must be stable within the period defined by minimum and maximum values of tDI-latch.

5.8.2.

Input Data Pre-Processing

Figure 5.3

Timing Diagram for Data Port D[3:0] and DSTBn

DSTBn

Data port output data

D[3:0]

tDI-latch

tDSTBn

tSTB

Keep stable

Data port input data

thold

min

max

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