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SAP5SD-B-G1-R 数据表(PDF) 52 Page - Renesas Technology Corp

部件名 SAP5SD-B-G1-R
功能描述  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  67 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SAP5SD-B-G1-R 数据表(HTML) 52 Page - Renesas Technology Corp

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
52
January 28, 2016
SOP 20
Pin #
SOP 16
Pin #
Name
Signal Name
Pin Configuration
Description
in Master/Repeater Mode
8
6
OSC1
OSC1
IN
Crystal oscillator / external clock input
9
7
U5R
U5R
OUT
Regulated 5V power supply
10
8
LTGN
LTGN
IN
AS-i Transmitter/Receiver output; to be
connected to ASi-
11
9
LTGP
LTGP
IN
AS-i Transmitter/Receiver input, to be
connected to ASi+ via reverse polarity
protection diode; input for the power fail
comparator
12
10
CDC
CDC
OUT
External buffer capacitor
13
11
UOUT
UOUT
OUT
Decoupled actuator/sensor power supply
14
12
PFAULT
None
IN
Not used
15
13
LED2
None
OUT
Not used
16
14
PSTBn
APF
OUT
AS-i power fail signal
17
15
D3
None
I/O
Not used
18
16
D2
None
I/O
Not used
19
-
P3
None
I/O
Not used
20
-
P2
None
I/O
Not used
5.19.3. Functional Description
In Master/Repeater Mode, the SAP5 provides a simple physical-layer interface function between the AS-i line and
an external binary channel.
The signal RX_DAT represents the Manchester-II-coded, re-synchronized equivalent of the telegram signal
received at the AS-i input channel. Polarity of that bit stream depends on the programmed operation mode
according to Table 5.26.
Table 5.26 Functional Differences between SAP5 Master and Repeater Modes
Modulation of Signal
RX_DAT if AS-i Power Fails
Loopback Mode
Polarity of signal RX_DAT
Master Mode 1
ON
ON
Active HIGH
Master Mode 2
OFF
ON
Active HIGH
Repeater Mode
OFF
OFF
Active LOW
Every AS-i telegram received is checked for consistency with the protocol specifications and timing jitters are
removed if they are within the specified limits. If a telegram error is detected, the output signal becomes inactive
for a time period defined by tBREAK (refer to Table 5.28).
The signal TX_DAT is directly forwarded to the AS-i line transmitter avoiding any additional logic delays.



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