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SAP5SD-B-G1-R 数据表(PDF) 23 Page - Renesas Technology Corp

部件名 SAP5SD-B-G1-R
功能描述  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  67 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SAP5SD-B-G1-R 数据表(HTML) 23 Page - Renesas Technology Corp

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
23
January 28, 2016
4.3.
Firmware Area Programming
In order to program one of the 5-bit cells in addresses 4 to 8 in the Firmware Area, a special master call according
to Table 4.3 must be applied, followed immediately by a DEXG or WPAR call. Write access to the Firmware Area
is possible as long as the Lock_EE_PRG flag is not set. The write procedure is started after receipt of the
DEXG/WPAR call. Completion of the write procedure can be observed at the status register S0 as described in
section 4.2.
The analog circuitry trim information (address 9 to 11) can be written by special test mode operation only.
It is not possible to read out the EEPROM data directly. However, AS-i-related configuration data such as
ID_Code can be read by the respective Read_ID_Code (RDID) master request.
Table 4.3
SAP5 EEPROM – User and Firmware Area Programming
Note: See table notes at the end of the table.
Internal
EEPROM
Address
EEPROM Cell Content
Programming Master Calls
User Area
0
A[4:0]
ADRA master call
1
ID1_Bit [3:0]
WID1 master call
2
ID1_Bit [3:0]
3
Not implemented
Firmware Area
4
Synchronous_Data_IO
I4
Set ID Code (RDIO) master call
1) + DEXG/WPAR master call 2)
ID_Bit [3:0]
I3 to I0
5
Inhibit_Write_ID1
I4
Set ID Code 2 (RID1) master call
1) + DEXG/WPAR master call 2)
ID2_Bit [3:0]
I3 to I0
6
P1_Delay_Activation
I4
Set IO Config (RDID) master call
1) + DEXG/WPAR master call 2)
IO_Bit [3:0]
I3 to I0
7
Lock_EE_PRG
I4
Set Control Code (RID2 ) master call
1) + DEXG/WPAR master call 2)
Delay_Mode
I3
Invert_Data_In
I2
Inhibit_BR01
I1
Inhibit_Watchdog
I0



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