SAP5SD-B-G1-R datasheet(13/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

OSCILLATOR /

PLL

The oscillator supports direct connection of 5.333MHz or 16.000MHz crystals with a dedicated load

capacity of 12pF and parasitic pin capacities of up to 8pF. The SAP5 automatically detects the

oscillation frequency of the connected crystal and controls the internal clock generator circuit

accordingly. After power-on reset, the SAP5 is set to 16.000MHz operation by default. After about

200µs, it will either switch to 5.333MHz operation or remain in the 16.000 MHz mode. The frequency

detection is active until the first AS-i telegram has been successfully received in order to ensure the

SAP5 has found the correct clock frequency setting. The detection result is locked thereafter to

increase resistance against burst or other interferences.

The oscillator unit also contains a Clock Watchdog circuit that can generate an unconditioned SAP5

reset if there has been no clock oscillation for more than approximately 20µs. This is to prevent

unpredicted SAP5 behavior if the clock signal is lost.

THERMAL

PROTECTION

The SAP5 is self-protected against thermal overload. If the silicon die temperature rises above

approximately 140°C for more than 2 seconds, the SAP5 detects thermal overheating, switches off

the electronic inductor, performs an SAP5 reset, and sets all analog blocks to power-down mode.

The 5V regulator is also turned off in this state; however, there will still remain a voltage of

approximately 3 to 3.5 V available at U5R that is derived from the internal start circuitry. If the over-

temperature condition is no longer present, the SAP5 resumes operation and performs an

initialization.

POWER FAIL

DETECTOR

The POWER FAIL DETECTOR observes the voltage at the AS-i line. It signals at the PSTBn/APF pin

when the voltage drops below approximately 22.5V. This is active in Master Mode only.

INPUT STAGE

All digital inputs, except the oscillator pins, have high voltage capabilities and pull-up features. For

more details see sections 5.3, 5.7, 5.8 and 7.1.

OUTPUT STAGE

All digital output stages, except the oscillator pins, have high voltage capabilities and are

implemented as NMOS open-drain buffers. Each pin can sink up to 10mA of current. See section 5.4.

3.2.

General Operational Modes

The SAP5 provides two operational modes: Slave Mode and Master/Repeater Mode. The operational mode that

becomes active is defined by programming the flag Master_Mode in the Firmware Area of the EEPROM (also see

Table 4.2). The EEPROM is read out at every initialization of the SAP5. Online mode switching is not provided.

The configurations in Table 3.1 apply:

Table 3.1

Assignment of Operational Modes

Selected Operational Mode

Master Mode Flag

Slave Mode

Master/Repeater Mode

In Slave Mode, the SAP5 operates as a fully featured AS-i slave IC according to AS-Interface Complete

Specification v3.0.

In Master/Repeater Mode, the SAP5 acts as physical layer transceiver. It translates a digital output signal from the

external master control logic (e.g., programmable logic controller (PLC), microprocessor, etc.) to a correctly

shaped, analog AS-i pulse sequence and vice versa. Every AS-i telegram received is checked for consistency

with the AS-i communication protocol specifications and if no errors were found, an appropriate Receive Strobe

signal is generated.

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