SAP5SD-B-G1-R datasheet(36/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

When running in Synchronous Data I/O Mode, the SAP5 also generates the Data Strobe (DSTBn) signal;

whereas the timing of input sampling and output buffering corresponds exactly to the standard operation (refer to

Figure 5.3 and Table 5.10).

5.8.4.

Support of 4I/4O Signaling in Extended Address Mode

In Extended Address Mode, the information bit I3 of the AS-i master telegram is used to distinguish between A

and B slaves that operate in parallel at the same AS-i slave address. For more detailed information, refer to the

AS-Interface Complete Specification V3.0.

In addition to the benefit of an increased address range, the cycle time per slave is increased in Extended

Address Mode from 5ms to 10ms and the useable output data is reduced from 4 to 3 bits. Because of the reduced

data bits, Extended Address Mode slaves can usually control a maximum of only 3 data outputs. The input data

transmission is not affected since the slave response still carries 4 data information bits in Extended Address

Mode.

Additionally, the SAP5 supports applications that require 4-bit wide output data in Extended Address Mode if the

application can tolerate further increased cycle times (e.g., push buttons and pilot lights). Such applications must

be directly characterized by a new Slave Profile 7.A.x.7, which is defined in the AS-Interface Complete Specifi-

cation (see section 9).

If the SAP5 is operated in Extended Address Mode and the Ext_Addr_4I/4O_Mode flag is set (= ‘1’) in the

EEPROM (refer to Table 4.2), it treats information bit I2 as the selector for two 2-bit wide data output banks:

• Bank_1 = D0/D1

• Bank_2 = D2/D3.

A master must consecutively transmit data to Bank_1 and Bank_2, toggling the information bit I2 in the respective

master calls. However, the SAP5 triggers a data output event (modification of the Data Output Ports and

generation of Data Strobe) as follows (see Table 5.13):

• If the Parallel_Out_4I/4O flag is set (= ‘1’) in the EEPROM (refer to Table 4.2), the SAP5 triggers a data

output event only if information bit I2 is equal to ‘0,’ in which case, new output data is issued at the Data

Port synchronously for both banks at the same time.

• If the Parallel_Out_4I/4O flag is not set (= ‘0’), the SAP5 triggers a data output event at every cycle.

However, depending on the information bit I2, only one bank of the Data Port gets refreshed.

SAP5SD-B-G1-R 数据表(PDF) 36 Page - Renesas Technology Corp