SAP5SD-B-G1-R datasheet(54/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

In Master/Repeater Mode, the SAP5 provides an AS-i power-fail detector. It consists of a comparator directly

connected to the LTGP pin that generates a logic signal if the voltage at the LTGP pin drops below VAPF (refer to

Table 5.28).

A subsequent digital signal processing of the comparator output signal is performed as follows:

• An anti-bouncing filter removes any signal states shorter than 6

µs. This is to eliminate the influence of AS-i

telegrams that are added onto the AS-i DC voltage.

• An additional anti-bouncing filter with different filter times for activation and deactivation of the power-fail

signal removes short power-fail pulses.

• The AS-i power-fail signal is provided directly active high as the signal APF.

• Additionally, in Master Mode, the AS-i power-fail signal modulates the RX_DAT signal; whereas the active

state is signaled by logic high level.

Table 5.28 Master/Repeater Mode Parameter

Parameter

Symbol

Min

Max

Unit

Loopback time in Master Mode

tLOOPBACK

4.9

6.5

µs

AS-i Power Fail voltage threshold

VAPF

21.5

23.5

Minimum activation time for signaling of AS-i Power Fail by use of the

RX_DAT signal

tAPF_RX_DAT

640

704

µs

Release time of the AS-i Power Fail state within the RX_DAT signal

tAPF_ON_RX_DAT

µs

Minimum activation time for signaling of AS-i Power Fail by use of the

APF signal

tAPF_APF

704

768

µs

AS-i Power Fail hold time

tHOLD_APF

µs

Delay time after return of the AS-i power

tAPF_OFF

128

µs

Break time in case of an erroneous AS-i signal

tBREAK

µs

Loopback time is the time difference between an edge in the MAN code of signal TX_DAT and the corresponding edge in the

Manchester-code of the signal RX_DAT. The voltage trigger level for measurement of the edge time is defined by VU5R/2. The actual

loopback time may be adjusted by programming the ID_Code_Extension_2 EEPROM register as described in Table 5.27.

In Master Mode, the AS-i Power Fail state is already signaled by the RX_DAT signal as soon as the power fail condition is true for a

time more than tAPF_RX_DAT. However, in order to start the APF minimum hold state (tHOLD_APF), the power fail condition must remain true

for another time period defined by tAPF_ON_RX_DAT. Otherwise, the RX_DAT signal returns to its idle state (logic low) immediately.

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