SAP5SD-B-G1-R datasheet(37/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

Table 5.13 Meaning of Master Call Bits I[3:0] with Ext_Addr_4I/4O_Mode = ‘1’

Master Call

Bit

Operation / Meaning

Parallel_Out_4I/4O = ‘0’

Parallel_Out_4I/4O = ‘1’

I2 = ‘0’

I2 = ‘1’

I2 = ‘0’

I2 = ‘1’

D2 = I0

D3 = I1

D1 = unchanged

D0 = unchanged

D2 = unchanged

D3 = unchanged

D1 = I1

D0 = I0

D2 = I0

D3 = I1

D1 = DO1_tmp

D0 = DO0_tmp

D2 = unchanged

D3 = unchanged

D1 = unchanged

D0 = unchanged

DO1_tmp = I1

DO0_tmp = I0

I2 =

Sel��-bitfortransmissiontoBank_1(D0/D1)/Bank_2(D2/D3)

I3 =

Sel��-bitforA-Slave/B-Slaveaddressing(seeTable3.2)

If I2 = ‘1’ then I0/I1 are directed to temporary data output registers DO0_tmp/DO1_tmp.

If I2 = ‘0’ then I0/I1 are directed to the data output registers D2/D3 and DO0_tmp/DO1_tmp are directed to data output registers

D0/D1.

In order to ensure that both Bank_1 and Bank_2 data are refreshed continuously, the SAP5 supervises the

alternation of the I2 Sel-bit by use of the 4I/4O Watchdog.

The 4I/4O Watchdog gets activated as soon as

•

The Communication Watchdog is activated (refer to section 5.17 and Table 5.22).

•

The SAP5 is operated in Extended Address Mode and the Ext_Addr_4I/4O_Mode flag is set (= ‘1’) in the

EEPROM.

•

Slave address is not equal to zero (0HEX).

•

No EEPROM write access is active.

•

The slave is activated, i.e. the Data_Exchange_Disable flag is cleared (‘0’).

If there is no alternation of the I2 bit for more than 327ms (+16ms) after the activation of the slave, the 4I/4O

Watchdog takes the following actions:

•

It generates Data and Parameter Strobe signals at the DSTBn and PSTBn pins with timing according to

Figure 5.2 and Figure 5.3.

•

After DSTBn and PSTBn strobe generation has finished, the 4I/4O Watchdog invokes an unconditioned

SAP5 reset. It sets the Data_Exchange_Disable flag and afterwards starts the SAP5 initialization

procedure, switching all Data and Parameter Outputs inactive.

Input data is captured and returned to the master at every cycle, independent of the value of information bit I2.

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