SAP5SD-B-G1-R datasheet(20/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

EEPROM

4.1.

Overview

The SAP5 features an on-chip EEPROM with typical write and read times according to Table 4.1.

Table 4.1

EEPROM Read and Write Times

Parameter

Symbol

Min

Max

Unit

Initialization read out time

tread_init

50.0

µs

Write time after ADRA master request

twrt_adra1

38.0

Write time after ADRA master request

twrt_adra2

12.5

Write time after WID1 master request (user access)

twrt_wid1u

38.0

Write time after WID1 master request (manufacturer access)

twrt_wid1m

25.0

Single cell write time

twrt_prgm

12.5

Time includes read out of the configuration block. If running in Safety Mode, the User/Firmware Area and the Safety Area will be

read out in parallel.

The Lock_EE_PRG flag is set.

The Lock_EE_PRG flag is not yet set.

Applies to the programming of data in both Firmware Area and Safety Area.

For security reasons, the memory area is structured in three independent data blocks and a single configuration

block containing the Security_Flag. The data blocks are named User Area, Firmware Area, and Safety Area,

which are defined in Table 4.2 and Table 4.4.

The Firmware Area contains all manufacturing-related configuration data; e.g., selection of optional features,

ID codes, etc. It can be protected against undesired data modification by setting the Lock_EE_PRG flag to ‘1’.

The User Area contains only such data that is relevant for changes at the final application (i.e., field installation of

slave module). Because the environment where modifications of the user data might become necessary can

sometimes be harsh and unpredictable, additional security has been added to the programming of the User Area,

ensuring a write access cannot result in an undetected corruption of EEPROM data.

The Safety Area contains the cryptographic code table for the Safety Mode.

The EEPROM cells in the User Area, Firmware Area, and Safety Area have a word width of 6 bits. The sixth bit is

not shown in Table 4.2 and Table 4.4. The sixth bit of each cell represents the odd parity of the respective data

word, providing an additional data security mechanism. The programming of the parity bit is performed

automatically during the EEPROM write process and cannot be influenced by the user. Each EEPROM read

process – particularly during initialization of the SAP5 – involves an evaluation of the parity bits. If an incorrect

parity bit is found in the User Area, the entire User Area data is treated as corrupted. The SAP5 returns to Slave

Address “0” and the ID_Code as well as the IO_Code are set to FHEX. If a false parity bit has been found in one or

more cells of the Firmware Area or the Safety Area, the status register bit S1 will be set (= ‘1’), signaling the same

state as if the input PFAULT had been set (see section 5.16).

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