SAP5SD-B-G1-R datasheet(45/67 Pages) RENESAS

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SAP51 / SAP5S Datasheet

January 28, 2016

If one or more of these errors occurs, the received telegram is treated as invalid. In this case, the UART will not

generate a Receive Strobe signal. It moves to asynchronous state and waits for a pause at the AS-i line input.

After a pause has been detected, the UART is ready to receive the next telegram.

Receive Strobe signals are generally used to validate the correctness of the received data. A Receive Strobe

starts the internal processing of a master request. If the UART was in asynchronous state before the signal was

generated, it transforms to synchronous state afterwards. If the received slave address matches the stored

address of the SAP5, the transmitter is turned on by the Receive Strobe pulse, allowing the output driver to settle

smoothly at the operation point (avoiding false pulses at the AS-i line).

5.15. Main State Machine

The Main State Machine controls the overall behavior of the SAP5. Depending on the configuration data stored in

the EEPROM, the State Machine activates one of the different SAP5 operational modes and controls the digital

I/O ports accordingly. In Slave Mode, it processes the received master telegrams and computes the contents of

the slave answer if required. Table 3.2 lists all master calls that are decoded by the SAP5 in Slave Mode. To

prevent the critical situation in which the SAP5 becomes locked in a prohibited state (e.g., due to exposure to

strong electromagnetic radiation), which could jeopardize the entire system, all prohibited states of the state

machine will lead to an unconditioned logic reset which is comparable to the AS-i call Reset_Slave (RES).

5.16. Status Registers

Table 5.21 shows the SAP5 status register content. The use of status bits S0, S1, and S3 is compliant with the

AS-Interface Complete Specification. Status bit S2 is not used. The status register content can be determined by

use of a Read_Status (RDST) master request (refer to Table 3.2).

Table 5.21 Status Register Content

Status Register Bit

Sx = 0

Sx = 1

EEPROM write accessible

Stored slave address volatile and/or EEPROM

access blocked (write in progress)

No Periphery Fault detected; EEPROM

Firmware Area and Safety Area content

consistent

Periphery fault detected; parity bit error in

EEPROM Firmware Area or Safety Area

Static zero

N/A

EEPROM content consistent

EEPROM contains corrupted data

Status bit S0 is set to ‘1’ as soon as a DELA master request was received and the slave address was not equal to “0” before the

request. It is also set for the entire duration of each EEPROM write access.

See section 4.2.

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