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SAP5SD-B-G1-R 数据表(PDF) 22 Page - Renesas Technology Corp

部件名 SAP5SD-B-G1-R
功能描述  AS-Interface Spec. V3.0 Compliant Universal AS-i IC
PDF  67 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

SAP5SD-B-G1-R 数据表(HTML) 22 Page - Renesas Technology Corp

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SAP51 / SAP5S Datasheet
© 2016 Integrated Device Technology, Inc.
22
January 28, 2016
Internal
EEPROM
Address
Bit Position
EEPROM Cell Contents
Description
Firmware Area
4
4
Synchronous_Data_IO
Synchronized Data I/O Mode
3 to 0
ID_Bit [3:0]
ID_Code
5
4
Inhibit_Write_ID1
ID_Code_Extension_1 is manufacturer configurable; refer to
section 5.20
3 to 0
ID2_Bit [3:0]
ID_Code_Extension_2
6
4
P1_Delay_Activation
If flag is set, the logic value at the parameter pin P1
determines whether the Delay_Mode function is active or
inactive; refer to Table 5.11
3 to 0
IO_Bit [3:0]
IO_Code
7
4
Lock_EE_PRG
Programming of the EEPROM Firmware region is possible
as long as this flag is not set (logic LOW).
3
Delay_Mode
Activates the Delay_Mode function, refer to Table 5.11
2
Invert_Data_In
All Data Port inputs are inverted.
1
Inhibit_BR01
If flag is set, the master call BR01 is not executed.
0
Inhibit_Watchdog
If flag is set, the watchdog is not activated.
8
4
P2_Sync_Activation
The Synchronized Data I/O Mode can be activated by
parameter bit P2 as described in Table 5.12.
3
Ext_Addr_4I/4O_Mode
4 Input/ 4 Output Mode in Extended Address Mode
2
Parallel_Out_4I/4O
Enables the parallel data output option in Extended Address
4I/4O Mode
1
Master_Mode
Master / Repeater Mode Flag
0
P0_Watchdog_Activation
The watchdog can be enabled / disabled by the logic value at
the parameter pin P0
9
4 to 0
Analog circuitry trim information
10
11



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