STLC1502 datasheet(23/81 Pages) STMICROELECTRONICS

23 / 81 page

23/81

STLC1502

6.5.1 The DMA Descriptors Chain

The Descriptor list is the mean the CPU and the DMA_MAC use to communicate each other in order to

transmit/receive frames on the cable. This list must be properly prepared before initiating any transfer

activity to/from the cable. The Descriptor is produced by the CPU and consumed by the DMA_MAC.

•

A Descriptor is a 16-bytes element which provides the DMA_MAC with information about how to

transmit/receive a single frame and how to report the transfer status back to the CPU.

•

A Descriptor can be stored in any main memory location with a 32-bit aligned address.

•

The first 3 words stored in a Descriptor are expected to be the values of the 3 DMA_MAC registers

describing a DMA transfer (DMA_Cntl, DMA_Addr and DMA_Next). When the DMA_MAC fetches a

Descriptor it loads this three values into its own corresponding registers.

•

The last word is to be used by the DMA_MAC to report the transfer status.

6.5.2 The Descriptor control bits

The Descriptor keeps information about a single frame transfer and how to access the next Descriptor.

The following discussion is related to 3 bits of the Descriptor: the VALID bit, the NXT_EN bit and the

NPOL_EN bit.

The Descriptor can be accessed simultaneously by the CPU and the DMA_MAC. This concurrent access

is synchronized by the VALID bit in the DMA_Cntl register. When the VALID bit is equal to 0 then the

CPU is the owner of the Descriptor. Otherwise the owner is the DMA_MAC. Since the Descriptor can be

accessed in write mode by the owner only at any time, race conditions are guaranteed to never happen.

The NXT_EN bit enables the fetch of the Next Descriptor. When the DMA_MAC finds this bit set to 0 then

its activity is considered to be completed as soon as the current descriptor DMA transfers have been

completed.

The NPOL_EN bit enables the DMA_MAC to keep polling for a non-valid Descriptor until its VALID bit is

set to one. When the DMA_MAC finds both the NPOL_EN bit and the VALID bit set to 0 then its activity is

considered to be completed.

DMA_Cntl

DMA_Addr

DMA_Next

Tx/Rx_Status

DMA_Cntl

DMA_Addr

DMA_Next

Tx/Rx_Status

DMA_Cntl

DMA_Addr

DMA_Next

Tx/Rx_Status

Frame 0

Frame 1

Frame n

. . .

Descr 1

Descr 2

Descr n

(4 X 4 Bytes)

STLC1502 数据表(PDF) 23 Page - STMicroelectronics

STLC1502 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载

链接网址

STLC1502 数据表(PDF) 23 Page - STMicroelectronics

STLC1502 数据表(HTML) 23 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表 下载

链接网址

数据表下载