STLC1502 datasheet(39/81 Pages) STMICROELECTRONICS

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STLC1502

Figure 12: IRQ control block

7.4.3 Interrupt register map [0x0C100000]

The base address of the timer register is 0x0C100000

The offset of any particular register from the base address is the following.

Address

R/W

Notes

Int.Base + 0x00

IRQStatus

For every IRQ interrupt cause,

a ‘1’ means an active pending

interrupt that has to be served

by the ARM

Int Base+ 0x04

IRQRawStatus

For every IRQ interrupt source,

a ‘1’ means an active pending

interrupt “before” the mask (w/

o considering the mask)

Int.Base + 0x08

IRQEnableSet

R/W

For every IRQ interrupt source,

a ‘0’ means that even if an

interrupt source is active, it has

to be stopped (masked). The

write operation of 1 to a given

bit, enable the corresponding

interrupt

INTERRUPT_MASK

Enable

nIRQ

Other Interrupt Bit Slices

IRQRawStatus

IRQStatus

Interrupt Source

Interrupt Pending

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