STLC1502 datasheet(25/81 Pages) STMICROELECTRONICS

25 / 81 page

25/81

STLC1502

With this approach every Descriptor will have the DMA_Next field pointing to the next Descriptor in the

chain (the last one will point to the first one), the NXT_EN bit, the VALID bit and the NPOL_EN bit on.

The DMA_MAC will keep fetching the Descriptors one by one until it finds one with its VALID bit set to off.

Every time the DMA_MAC completes a Descriptor (frame) it saves the transfer status into TxRx_Status,

it turns its VALID bit to off and raises the TX_CURR_DONE interrupt bit.

6.5.8 Frames reception (RX)

The frame reception process is something that needs to be activated at the beginning and kept always

running. For this reason the closed Descriptor list (see above) is much more useful than the open list

approach.

Again, with this approach every Descriptor will have the DMA_Next field pointing to the next Descriptor in

the chain (the last one will point to the first one), the NXT_EN bit, the VALID bit and the NPOL_EN bit on.

The CPU starts the transfer activity loading the DMA Next register of the DMA_MAC with the physical

location of the first Descriptor and set the DMA Start register enable bit to on.The DMA_MAC will start

fetching the Descriptors one by one, driven by the frames reception from the line. Every time the

DMA_MAC completes a Descriptor (frame) it saves the transfer status into TxRx_Status, it turns its

VALID bit to off and raises the TX_CURR_DONE interrupt bit.

Eventually, the DMA_MAC will be faster than the CPU, it will wrap around the Descriptor chain and find a

Descriptor still invalid.

Then the DMA_CNT keeps polling the invalid descriptor, raising each time the TX_NEXT interrupt bit (if

enabled), until some Descriptor gets available (note that in this case some frame could be lost). In the

meantime the CPU should consume the frames received and set the VALID bit to on of all the Descriptor

released.

As soon as the DMA_CNT finds the Descriptor valid again, it will be able to complete the transfer and to

fetch the next Descriptor.

6.5.9 Ethernet block Register Map [0x0C680000]

The base address of the Ethernet registers is 0x0C680000

The memory map of the Dual MAC Ethernet block is shown below:

Address

Notes

DMA_MAC1 Eth_base1=0x0C680000

Eth_base1+ 0x0000

DMA_ST&CNTL

DMA Status and Control Register

Eth_base1+0004

DMA_INT_EN

DMA Interrupt Sources Enable Register

Eth_base1+0008

DMA_INT_STAT

DMA Interrupt Status Register

Eth_base1+000C

Reserved

Eth_base1+ 0x0010

RX_DMA_START

RX DMA start Register

STLC1502 数据表(PDF) 25 Page - STMicroelectronics

STLC1502 数据表(HTML) 25 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载