STLC1502 datasheet(50/81 Pages) STMICROELECTRONICS

50 / 81 page

STLC1502

50/81

Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even parity bit

will be set, if the modulo-2-sum of the eight data bits is 1. An odd parity bit will be cleared in this case.

The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity bit itself will be

stored in bit 8 of the ASCRx-Buffer register.

In wake-up mode, received frames are only transferred to the receive buffer register if the ninth bit (the

wake-up bit) is 1. If this bit is 0, no receive interrupt request will be activated and no data will be trans-

ferred. This feature may be used to control communication in multi-processor systems. When the master

processor wants to transmit a block of data to one of several slaves, it first sends out an address byte

which identifies the target slave. An address byte differs from a data byte in that the additional ninth bit is

a 1 for an address byte and a 0 for a data byte, so no slave will be interrupted by a data byte. An address

byte will interrupt all slaves (operating in 8-bit data + wake-up bit mode), so each slave can examine the

8 least significant bits (LSBs) of the received character (the address). The addressed slave will switch to

9-bit data mode, which enables it to receive the data bytes that will be coming (with the wake-up bit

cleared). The slaves that are not being addressed remain in 8-bit data + wake-up bit mode, ignoring the

following data bytes.

9-bit data frame

7.7.2 Baud rate generation

The UART has its own dedicated 16-bit baud rate generator with 16-bit reload capability.

The baud rate generator is clocked with the CPU clock. The timer counts downwards and can be started

or stopped by the Run bit in the ASCControl register. Each under-flow of the timer provides one clock

pulse. The timer is reloaded with the value stored in its 16-bit reload register each time it underflows. The

ASCBaudRate register is the dual-function baud rate generator/reload register. A read from this register

returns the content of the timer; writing to it updates the reload register. An auto-reload of the timer with

the content of the reload register is performed each time the ASCBaudRate register is written to. How-

ever, if the Run bit is 0 at the time the write operation to the ASCBaudRate register is performed, the

timer will not be reloaded until the first CPU clock cycle after the Run bit is 1.

The baud rate generator provides a clock at 16 times the baud rate. The baud rate and the required

reload value for a given baud rate can be determined by the following formula:

Baudrate = fCPU/(16 *ASCBaudRate)

7.7.3 The timeout interrupt

A timeout counter register provides timeout interrupt on the receive path.

Whenever the rxfifo has got something in it, the timeout counter will decrement until something happens

Start

bit

1st

bit

stop

bit

9th

bit

stop

2nd

- Data bit (D7)

- Parity bit

(LSB)

- Wake up bit

STLC1502 数据表(PDF) 50 Page - STMicroelectronics

STLC1502 数据表(HTML) 50 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载