STLC1502 datasheet(53/81 Pages) STMICROELECTRONICS

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STLC1502

7.9 HPI

The HPI is dual port SRAM based, with control that generates an interrupt when a message is sent. The DPRAM

is implemented on chip and has a message buffer size of 256 bytes for each direction. Input buffer is used for

messages from Host Processor to Stradivarius. Output buffer is used for messages from Stradivarius to Host

Processor.

•

The external bus interface of the HPI is compatible with Motorola MPC850 network processor. The

data bus width is 8 bits.

•

A status register, an index register (for the host processor), an interrupt mask register, and a mes-

sage buffer are required for both input and output transactions.

•

The Input Status Register (ISR) is set by the Host Processor by writing 0x01 and cleared by writing

0x00 to the location. It is cleared by ARM by writing anything to it.

•

The Output Status Registers (OSR) is set by the ARM by writing 0x01 and cleared by writing 0x00. It

is cleared by the Host Processor by writing anything to it.

•

The Input and Output Index Registers (IIR & OIR respectively) are reset to their starting value by writ-

ing 0x00 to their respective addresses. They can also be cleared by the Host Processor by writing

anything to them.

•

The Input Interrupt Mask Register (IIM) resets to 0x00, causing the Mask to be set (active low). This

means that before the ARM can receive message ready interrupts from the Host Processor, this reg-

ister must be written with 0x0001 (by ARM) to unmask the interrupt.

•

The Output Interrupt Mask Register (OIM) resets to 0x00, causing the Mask to be set (active low).

This means that before the Host Processor can receive message ready interrupts from the ARM, this

•

The Input and Output Message buffers are each 256 bytes long and 1 byte wide (an overflow in the

index register will not write to the other message buffer, but will start to overwrite the current mes-

sage buffer).

•

Addressing of the Input and Output Message Buffers by the Host Processor is implemented indirectly

via the Input and Output Index Registers. An external interrupt signal is generated when the output

status register is set by the ARM7. An ARM7 interrupt signal is generated when the input status reg-

ister is set by the Host Processor.

7.9.1 Send Message from Host Processor to ARM

•

Read Input Status Register. If h01, the ARM has not read out the last message. If 0x00, the ARM has

read the last message and the Input Message Buffer is available for use.

•

Clear Input Index Reg by writing any value to its address (b.100).

•

Write message into Input Message Buffer by consecutively writing to its address (b.111). Each write

will cause the Input Index Register to increment by 1 and access another byte location.

•

Write 0x01 to Input Status Register (address b.011) to interrupt the ARM

GPIO_regBase+ 0x08

Data

R/W

This register allows GPIO data

output setting

GPIO_regBase+ 0x0C

Status

R/W

Key data flag

GPIO_regBase+ 0x10

Key

Key value

Address

Name

R/W

Notes

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