STLC1502 datasheet(46/81 Pages) STMICROELECTRONICS

46 / 81 page

STLC1502

46/81

software).

Note: In 10-bit addressing mode, the comparison includes the header sequence (11110xx0) and the two

most significant bits of the address.

•

Header matched (10-bit mode only): the interface generates an acknowledge pulse if the ACK bit

is set.

•

Address not matched: the interface ignores it and waits for another Start condition.

•

Address matched: the interface generates in sequence:

• Acknowledge pulse if the ACK bit is set.

• EVFand ADSL bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register, holding the SCL line low. Next, read the DR register to

determine from the least significant bit (Data Direction Bit) if the slave must enter Receiver or Transmitter mode.

In 10-bit mode, after receiving the address sequence the slave is always in receive mode. It will enter transmit

mode on receiving a repeated Start condition followed by the header sequence with matching address bits and

the least significant bit set (11110xx1).

Slave Receiver

After the address reception and SR1 register has been read, the slave receives bytes from the SDA line

into the DR register via the internal shift register. After each byte the interface generates in sequence:

– Acknowledge pulse if the ACK bit is set

– EVF and BTF bits are set with an interrupt if the ITE bit is set.

Then the interface waits for a read of the SR1 register followed by a read of the DR register, holding the

SCL line low.

Slave Transmitter

After the address reception and the SR1 register has been read, the slave sends bytes from the DR reg-

ister to the SDA line via the internal shift register. The slave waits for a read of the SR1 register followed

by a write in the DR register, holding the SCL line low.

When the acknowledge pulse is received:

– The EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.

Closing slave communication

After the last data byte is transferred a Stop Condition is generated by the master. The interface detects

this condition and sets:

– EVF and STOPF bits with an interrupt if the ITE bit is set.Then the interface waits for a read of the SR2

Error Cases

– BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the EVF and the

BERR bits are set with an interrupt if the ITE bit is set. If it is a Stop then the interface discards the data,

released the lines and waits for another Start condition. If it is a Start then the interface discards the data

and waits for the next slave address on the bus.

– AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set with an interrupt if the

ITE bit is set.

Note: In both cases, SCL line is not held low; however, SDA line can remain low due to possible «0» bits

transmitted last. It is then necessary to release both lines by software.

How to release the SDA / SCL lines:

•

Set and subsequently clear the STOP bit while BTF is set.

STLC1502 数据表(PDF) 46 Page - STMicroelectronics

STLC1502 数据表(HTML) 46 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载