STLC1502 datasheet(49/81 Pages) STMICROELECTRONICS

49 / 81 page

49/81

STLC1502

7.7 UART-Universal Asynchronous Receiver Transmitter

The UART provides a serial data communication with transmit and receive channels that can operate

concurrently to handle a full-duplex operation. Two internal FIFOs for transmitted and received data,

deep 16 and wide 8 bits, are present; these FIFOs can be enabled or disabled through a register. Inter-

rupts are provided to control reception and transmission of serial data.

The clock for both transmit and receive channels is provided by an internal baud rate generator that

divides its input clock by any divisor value from 1 to 2 16 - 1.

7.7.1 Operation

The UART supports full-duplex asynchronous communication, where both the transmitter and the

receiver use the same data frame format and the same baud rate. Data is transmitted on the TXD pin and

received on the RXD pin.

Data frames

8-bit data frames either consist of:

•

eight data bits D0-7 (by setting the Mode bit field to 001);

•

seven data bits D0-6 plus an automatically generated parity bit (by setting the Mode bit field to 011).

Parity may be odd or even, depending on the ParityOdd bit in the ASCControl register. An even parity bit

will be set, if the modulo-2-sum of the seven data bits is 1. An odd parity bit will be cleared in this case.

The parity error flag (ParityError) will be set if a wrong parity bit is received. The parity bit itself will be

stored in bit 7 of the ASCRx-Buffer register.

8-bit data frame

9-bit data frames either consist of:

•

nine data bits D0-8 (by setting the Mode bit field to 100)

•

eight data bits D0-7 plus an automatically generated parity bit (by setting the Mode bit field to 111)

•

eight data bits D0-7 plus a wake-up bit (by setting the Mode bit field to 101)

I2C_regBase+ 0x2C

I2CCCR

R/W

I2C Clock Control register.

I2C_regBase+ 0x30

I2COAR1

R/W

I2C Own Address register

I2C_regBase+ 0x34

I2COAR2

R/W

I2C Own Address register

I2C_regBase+ 0x38

I2CDR

R/W

I2C Data I/O register.

Address

Name

R/W

Notes

Start

bit

1st

bit

stop

bit

8th

bit

stop

2nd

-Data bit (D7)

-Parity bit

(LSB)

STLC1502 数据表(PDF) 49 Page - STMicroelectronics

STLC1502 数据表(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

数据表下载