STLC1502 datasheet(45/81 Pages) STMICROELECTRONICS

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STLC1502

By default, it operates in slave mode. The interface automatically switches from slave to master after it

generates a START condition and from master to slave in case of arbitration loss or a STOP generation,

allowing then Multi-Master capability.

In Master mode, it initiates a data transfer and generates the clock signal. A serial data transfer always

begins with a start condition and ends with a stop condition. Both start and stop conditions are generated

in master mode by software.

In Slave mode, the interface is capable of recognizing its own address (7 or 10 bits), and the General Call

address. The General Call address detection may be enabled or disabled by software.

Data and addresses are transferred as 8-bit bytes, MSB first. The first byte(s) following the start condition

contain the address (one in 7-bit mode, two in 10-bit mode). The address is always transmitted in Master

mode. A 9th clock pulse follows the 8 clock cycles of a byte transfer, during which the receiver must send

an acknowledge bit to the transmitter.

•

Acknowledge may be enabled and disabled by software. The I 2 C interface address and/or general

call address can be selected by software. The speed of the I 2 C interface may be selected between

Standard (0-100KHz) and Fast I2C (100-400KHz).

•

In transmitter mode the interface holds the clock in low before transmission to wait for the microcon-

troller to write the byte in the Data Register.

•

In receiver mode: the interface holds the clock line low after reception to wait for the microcontroller

to read the byte in the Data Register.

•

The SCL frequency (Fscl) is controlled by a programmable clock divider which depends on the I 2 C

bus mode.

•

When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this

case, the value of the external pull-up resistor used depends on the application.

7.6.3 Functional Description

Refer to the CR, SR1 and SR2 registers in register map section for the bit definitions.

By default the I 2 C interface operates in Slave mode (M/SL bit is cleared) except when it initiates a trans-

mit or receive sequence. First the interface frequency must be configured using the FRi bits in the OAR2

7.6.3.1 Slave mode

As soon as a start condition is detected, the address is received from the SDA line and sent to the shift

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